A Phase Change Memory as a Secure Main Memory
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29-01-2011, 07:32 PM


A Phase Change Memory as a Secure Main Memory
A Seminar Report
by
Abdul Nassar A A
M105101
Department of Computer Science & Engineering
College of Engineering Trivandrum
Kerala - 695016
2010-11


.pdf   A Phase Change Memory as a Secure main memory.pdf (Size: 220.44 KB / Downloads: 122)


Contents
1 Introduction 5
2 PCM Technology 6
2.1 History and background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Memory cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Wear and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 PCM attributes 10
4 A secure PCM based main memory 11
4.1 Security principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.1 Invisible PA-to-PCMA translation is required . . . . . . . . . . . . . . . 11
4.1.2 PA-to-PCMA translations must dynamically . . . . . . . . . . . . . . . . 11
4.2 Principles of a practical secure PCM-based main memory . . . . . . . . . . . . 11
4.2.1 PA-to-PCMA translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 PA-to-PCMA region address translation . . . . . . . . . . . . . . . . . . 11
4.2.3 PA-to-PCMA region displacement translation . . . . . . . . . . . . . . . 11
4.2.4 Dynamically changing PA-to-PCMA translation . . . . . . . . . . . . . . 12
4.2.5 How to modify PA-to-PCMA translation . . . . . . . . . . . . . . . . . . 12
4.2.5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 PCM memory controller 13
5.1 Write endurance and region size . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Memory controller constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Swapping memory regions logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Extra PA-to-PCMA translation latency . . . . . . . . . . . . . . . . . . . . . . 14
5.5 The random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Write Endurance for conventional applications . . . . . . . . . . . . . . . . . . 14
6 Future trends in PCM technology 15
6.1 Economic feasibility of PCM main memory . . . . . . . . . . . . . . . . . . . . . 15
6.2 Page mode is compatible with security . . . . . . . . . . . . . . . . . . . . . . . 15
6.3 Limiting extra write trac overhead . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Applications 16
8 Conclusion 18


Abstract
Phase Change Memory (PCM) technology appears as more scalable than DRAM technology.
As PCM exhibits access time slightly longer but in the same range as DRAMs, several recent
studies have proposed to use PCMs for designing main memory systems. Unfortunately PCM
technology su ers from a limited write endurance; typically each memory cell can be only be
written a large but still limited number of times (107 to 109 writes are reported for current
technology). Till now, research proposals have essentially focused their attention on designing
memory systems that will survive to the average behavior of conventional applications. However
PCM memory systems should be designed to survive worst-case applications, i.e., malicious
attacks targeting the physical destruction of the memory through overwriting a limited number
of memory cells.This seminar and presentation paper proposes the design of a secure PCM-based main memory
that would by construction survive to overwrite attacks.

1 Introduction
Phase Change Memory (PCM) technology appears as a promising technology for designing
main memory in future computer systems. PCM presents advantages over DRAMs in terms of
static energy consumption as well as integration scalability for future technologies generations;
for instance, anticipates durance, i.e., a PCM memory cell can only support a limited number
of writes and exceeding this limit might impair its correct functioning. The reported write
endurances for PCM memory vary between 107 and 109 writes on a single cell. Such a limited
endurance has been recognized as issue for the design of PCM-based main memory systems.
Several propositions have been made to allow a PCM main memory to survive the anticipated
lifetime of a computer system ,i.e., 10 to 20 years, in the context of general applications. At
the exception of these studies completely ignore the security breach that the limited write
endurance of PCM components would create in a main memory. PCM components for main
memory would create a main memory through a very simple program overwriting the same
memory cells again and again. The potential attack is particularly simple to mount. It can
be run by any user without any execution privilege. It is seen that their Region Based Start
Gap scheme would survive a few months to a naive overwrite attack consisting in constantly
overwriting the same physical memory address. However, the Region Based Start Gap (RBSG)
scheme considered in would not survive more than a few days to a slightly more complex attack
based on the birthday paradox. More over the RBSG scheme a RBSG scheme supporting page
mode would even be less endurant to an overwrite attack.This paper proposes the design of a
secure main PCM memory. In order to prevent a malicious user to overwrite some memory
cells, the physical memory address (PA) manipulated by the computer system is not the same
as the PCM memory address (PCMA) . PCMA is made invisible from the rest of the computer
system. The PCM memory controller is in charge of the PA-to-PCMA translation. Hiding
PCMA alone does not prevent a malicious user to blindly overwrite some PCM memory blocks.
Therefore in the secure PCM-based main memory, PA-to-PCMA translation is continuously
modi ed through a random process. This prevents a malicious user to overwrite some PCM
memory words, it also uniformizes the write pressure on the overall memory for every possible
type of workloads. For implementing the PA-to-PCMA translation, the PCM memory controller
implements a translation table and needs an ecient random number generator. As an example,
for write endurance in the 32M range, our study shows that associating a single translation
table entry with a 4K memory blocks region should be sucient. Provided one extra write
per 8 program generated writes, our scheme would resist an overwrite attack for 62 % of the
expected total memory lifetime. However, endurance to overwrite attacks is obtained at the
cost of some performance decrease on applications limited by the main memory bandwidth
since one extra block read and one extra memory block write is generated every eight memory
block writes. The security also limits the number of possible program-generated writes on the
memory to 8/9 th of the total number of possible writes on the memory.

2 PCM Technology
Given the still speculative state of PCM technology, researchers have made several di erent
manufacturing and design decisions. The survey details of device and circuit prototypes pub-
lished within the last 5 years.
2.1 History and background
In the 1950s and 1960s, Dr. Stanford Ovshinsky began researching the properties of a class of
amorphous materials. Amorphous materials are those materials that do not exhibit a de nite,
ordered crystalline structure. By 1968, he reported that certain glasses exhibited a reversible
change in resistivity upon a change in phase. In 1969, he also reported a corresponding change
in re
ectivity that could be induced by laser in an optical storage media. By 1970, the com-
pany he and his wife Dr. Iris Ovshinsky founded, Energy Conversion Devices (ECD), published
the results of a collaboration with Intel's Gordon Moore. The September 28th, 1970 issue of
Electronics2 featured the world's rst Phase Change Memory, a 256 bit semiconductor device.
Memory (PCM) is a term used to describe a class of non-volatile memory devices that employ
a reversible phase change in materials to store information. Matter can exist in various phases
such as solid, liquid, gas, condensate and plasma. PCM exploits di erences in the electrical
resistivity of a material in di erent phases. This paper describes the basic technology and
capabilities of PCM. History and background In the 1950s and 1960s, Dr. Stanford Ovshinsky
began researching the properties of a class of amorphous materials. Amorphous materials are
those materials that do not exhibit a de nite, ordered crystalline structure. By 1968, he re-
ported1 that certain glasses exhibited a reversible change in resistivity upon a change in phase.
In 1x969, he also reported a corresponding change in re
ectivity that could be induced by laser
in an optical storage media. By 1970, the company he and his wife Dr. Iris Ovshinsky founded,
Energy Conversion Devices (ECD), published the results of a collaboration with Intel's Gor-
don Moore. The September 28th, 1970 issue of Electronics2 featured the world's rst Phase
Change Memory, a 256 bit semiconductor device. Nearly 30 years later, ECD formed a new
subsidiary, Ovonyx, a joint venture between ECD and Tyler Lowery, the former CTO, COO
and Vice-Chairman of Micron Technology. In February 2000, Intel and Ovonyx announced
a collaboration and licensing agreement that spawned the modern age of research and devel-
opment in PCM. In December of 2000, STMicroelectronics ("ST") and Ovonyx also began a
collaboration. By 2003, the three companies had joined forces to accelerate progress on the
technology by avoiding duplication in basic, pre-competitive R & D and through expanding
the research scope. In 2005, ST and Intel agreed to co-develop a 90 nm PCM technology. In
2007, ST and Intel announced their intention to form a new
ash company called Numonyx.
In the intervening years since that rst work in 1970, much progress has been made in semi-
conductor manufacturing technology, enabling the practical development of PCM. Also during
that time period, phase change materials were perfected for high volume use in rewritable CDs
and DVDs. Today, most DVD-RAMs available today use the exact same PCM attributes and
capabilities Phase Change Memory blends the attributes commonly associated with NOR-type

ash, memory NAND-type
ash memory, and RAM or EEpROM.
2.2 Memory cell
As shown in Figure 1, the PCM storage element is comprised of two metal electrodes separated
by a resistive heater and a chalcogenide, the phase change material. Ge2Sb2Te5 (GST) is most
commonly used, but other chalcogenides may o er higher resistivity and improve the device's
electrical characteristics. Nitrogen doping increases resistivity and lowers programming current
6
Figure 1: PCM Memory Elements.
while GS may o er faster phase changes. As shown in Figure 2, PCM cells are 1T/1R devices,
comprised of the resistive storage element and an access transistor. Access is typically controlled
by one of three devices: eld-e ect transistor (FET), bipolar junction transistor (BJT), or diode.
In future, FET scaling and large voltage drops across the cell may adversely a ect reliability
for unselected wordlines. BJTs are faster and expected to scale more robustly without this
vulnerability. Diodes occupy smaller areas and potentially enable greater cell densities, but
require higher operating voltages. Phase changes are induced by injecting current into the
resistor junction and heating the chalcogenide. Current and voltage characteristics of the
chalcogenide are identical regardless of its initial phase, which lowers programming complexity
and latency. The amplitude and width of the injected current pulse determine the programmed
Figure 2: PCM Memory Cell.
7
Figure 3: PCM Memory Elements.
state as shown in Figure 3.
2.3 Operation
The access transistor injects current into the storage material and thermally induces phase
change, which is detected as a programmed resistance during reads. Logical data values are
captured by the resistivity of the chalcogenide. A high, short current pulse increases resistivity
by abruptly discontinuing current, quickly quenching heat generation, and freezing the chalco-
genide into an amorphous state (i.e., reset). A moderate, long current pulse reduces resistivity
by ramping down current, gradually cooling the chalcogenid and inducing crystal growth (i.e.,
set). Requiring longer current pulses, set latency determines write performance. Requiring
higher current pulses, reset energy determines write power. Prior to reading the cell, the bit-
line is precharged to the read voltage. If a selected cell is in a crystalline state, the bit line
is discharged with current
owing through the storage element and access transistor. Other-
wise, the cell is in an amorphous state, preventing or limiting bit line current. Cells that store
multiple resistance levels might be implemented by leveraging intermediate states, in which
the chalcogenide is partially crystalline and partially amorphous. Smaller current slopes (i.e.,
slow ramp down) produce lower resistances and larger slopes (i.e., fast ramp down) produce
higher resistances. Varying slopes induce partial phase transitions changing the size or shape of
the amorphous material produced at the contact area, giving rise to resistances between those
observed from the fully amorphous or the fully crystalline chalcogenide. The diculty and high
latency of di erentiating between a large number of resistances may constrain such multilevel
cells (MLC) to a small number of bits per cell.
8
2.4 Wear and Endurance
Writes are the primary wear mechanism in PCM. When injecting current into a volume of
phase change material, thermal expansion and contraction degrades the electrode-storage con-
tact, such that programming currents are no longer reliably injected into the cell. Since material
resistivity is highly dependent on current injection, current variability causes resistance vari-
ability. This greater variability degrades the read window, the di erence between programmed
minimum and maximum resistance. Write endurance, the number of writes performed before
the cell cannot be programmed reliably, ranges from 1E+04 to 1E+09. Write endurance de-
pends on process and di ers across manufacturers. Relative to Flash, PCM is likely to exhibit
greater write endurance by at least two to three orders of magnitude; Flash cells can sustain
only 1E+05 writes. The ITRS roadmap project and implimentations improved endurance of 1E+12 writes at 32nm
With wear reduction and leveling techniques, PCM write limits may not be exposed to the
system during a memory's lifetime.
9
3 PCM attributes
This new class of non-volatile memory brings together the best attributes of NOR, NAND and
RAM.
1. Bit-alterable:
Like RAM or EEpROM, PCM is bit alterable. Flash technology requires a separate erase
step in order to change information. Information stored in bit-alterable memory can be
switched from a one to zero or zero to a one without a separate erase step.
2. Non-volatile:
Like NOR
ash and NAND
ash, PCM is nonvolatile. RAM, of course, requires a con-
stant power supply, such as a battery backup system, to retain information. DRAM
technologies also su er from susceptibility to so-called "soft errors" or random bit cor-
ruption caused by alpha particles or cosmic radiation. Early testing results conducted by
Intel on multimegabit PCM arrays for long term data retention show excellent results.
3. Read speed:
Like RAM and NOR-type
ash, the technology features fast random access times. This
enables the execution of code directly from the memory, without an intermediate copy to
RAM. The read latency of PCM is comparable to single bit per cell NOR
ash, while the
read bandwidth can match DRAM. In contrast, NAND
ash su ers from long random
access times on the order of 10s of microseconds that prevent direct code execution.
4. Write/erase speed:
PCM is capable of achieving write speeds like NAND, but with lower latency and with
no separate erase step required. NOR
ash features moderate write speeds but long erase
times. As with RAM, no separate erase step is required with PCM, but the write speed
(bandwidth and latency) does not match the capability of RAM today. The capability
of PCM is expected, however, to improve with each process erase speed PCM is capable
of achieving write speeds like NAND, but with lower latency and with no separate erase
step required. NOR
ash features moderate write speeds but long erase times. As with
RAM, no separate erase step is required with PCM, but the write speed (bandwidth
and latency) does not match the capability of RAM today. The capability of PCM is
expected, however, however, to improve with each process generation as the PCM cell
area decreases. Scaling is the fth area where PCM will o er a di erence. Both NOR and
NAND rely on memory structures which are dicult to shrink at small lithos. This is due
to gate thickness remaining constant and the need for operation voltage of more than 10V
while the operation of CMOS logic has been scaled to 1V or even less. This scaling e ect
is often referred to as Moore's Law, where memory densities double with each smaller
generation. With PCM, as the memory cell shrinks, the volume of GST material shrinks
as well, providing a truly scalable solution. PCM employs a reversible phase change
phenomenon to store information through a resistance change in di erent phases of a
material. Advances in memory technology and pioneering work conducted by Numonyx
has moved the technology to the forefront of the memory industry R & D activity. PCM
o ers a combination of some of the best attributes of NOR
ash, NAND
ash, EEpROM
and RAM in a single memory device. These capabilities uniquely combined with the
potential for lower memory subsystem costs could potentially create new applications
and memory architectures in a wide range of systems.
10
4 A secure PCM based main memory
4.1 Security principles
4.1.1 Invisible PA-to-PCMA translation is required
If a malicious attacker knows the PA-to-PCMA translation then for a given PCM memory
block B, he/she is able to gure out the address of the physical memory block that is mapped
on B. If the PA-to-PCMA translation is made invisible from the outside of the PCM memory
then the attacker can not retrieve the address of the physical memory block mapped on a given
memory block.
4.1.2 PA-to-PCMA translations must dynamically
Our analysis of the RBSG scheme has shown that, in order to resist a birthday paradox attack,
the PA to PCMA translation of any physical block B has to be modi ed with a frequency
largely higher than one time every Wmax possible writes on B. The PA-to-PCMA translation
changes should be completely unpredictable from the outside of the PCM memory; in particular
there should be no restrictions on the new translation.
4.2 Principles of a practical secure PCM-based main memory
4.2.1 PA-to-PCMA translation
In the secure PCM-based main memory the PA-to-PCMA translation is performed by the PCM
memory controller through the use of a translation table. For a physical memory block B, the
address of the corresponding PCM block is computed from an entry read in the translation
table and the address B. The PA to PCMA translation must perform a one-to-one address
translation from the physical address space to PCM address space. The simplest mapping
would be to associate a translation table entry with each physical memory block and ensuring
that the translation is a one-to-one block mapping. Such one-to-one block mapping appears as
unpractical so associate a single translation table entry with a region of R contiguous memory
blocks; for instance if 4K contiguous memory blocks are mapped by a single entry, 64K entries
are sucient to map 16 GBytes. Such a single translation for a large region was already
proposed in the context of wear leveling for conventional applications
4.2.2 PA-to-PCMA region address translation
Initializing at boot time the translation table T with a one-to-one region mapping is unprac-
tical. Instead of such an initialization,assume that at initialization time, the translation table
T is initialized with only zeros, but that some computation is performed at runtime in addi-
tion to the read of the translation table. If memory regions are numbered from 0 to N
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