A hardware implementation of an MP3 decoder
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07-10-2010, 09:51 AM




Abstract

In recent years, several commercial system-on-chip solutions for MP3 decoding have been developed. They are usually built around a specialised RISC processor with an instruction set suitable for MPEG audio decoding. The purpose of this project and implimentation is to evaluate and implement the different parts of the MP3 decoding without using a processor core. Instead, small hardware accelerators are implemented for each stage in the decoding chain. Using specialised logic could lower the power consumption that is of most importance in handheld devices. The implementation is based on Thomas Lenarts C-code for MP3 decoding.

INTRODUCTION

During the last years the usage of the MPEG-1 layer- III (mp3) audio codec has exploded, and a large part of the global bandwidth consumed is used for transferring layer- III compressed audio data, or in casual language ”mp3 files”. During the first years of widespread mp3 usage, software decoders were the most common, but during the last couple of years portable and other stand-alone players have gained in popularity. Particularly in hand held devices dedicated hardware for accelerating the mp3-decoding process, in terms of clock cycles and power usage, is important. This report describes an attempt to create an efficient dedicated mp3- decoder in hardware.

For more details, please visit
mp3-techprogrammer/docs/fpga_report.pdf
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