ARM architecture
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21-02-2011, 09:53 AM


ARM architecture
Brief history of ARM

• ARM is short for Advanced Risc Machines Ltd.
• Founded 1990, owned by Acorn, Apple and VLSI
• Known before becoming ARM as computer manufacturer
Acorn which developed a 32-bit RISC processor for it’s own
use (used in Acorn Archimedes)
Why ARM here?
• ARM is one of the most licensed and thus widespread
processor cores in the world
• Used especially in portable devices due to low power
consumption and reasonable performance (MIPS / watt)
• Several interesting extensions available or in development like
Thumb instruction set and Jazelle Java machine
ARM
• Processor cores: ARM6, ARM7, ARM9, ARM10, ARM11
• Extensions: Thumb, El Segundo, Jazelle etc.
• IP-blocks: UART, GPIO, memory controllers, etc
ARM architecture
• ARM:
• 32-bit RISC-processor core (32-bit instructions)
• 37 pieces of 32-bit integer registers (16 available)
• Pipelined (ARM7: 3 stages)
• Cached (depending on the implementation)
• Von Neuman-type bus structure (ARM7), Harvard (ARM9)
• 8 / 16 / 32 -bit data types
• 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
• Simple structure -> reasonably good speed / power consumption ratio
ARM7 internals
ARM core modes of operation:

• User (usr): Normal program execution state
• FIQ (fiq): Data transfer state (fast irq, DMA-type transfer)
• IRQ (iqr): Used for general interrupt services
• Supervisor (svc): Protected mode for operating system support
• Abort mode (abt): Selected when data or instruction fetch is aborted
• System (sys): Operating system ‘privilege’-mode for user
• Undefined (und): Selected when undefined instruction is fetched
ARM7 register set
• Register structure depends on mode of operation
• 16 pieces of 32-bit integer registers R0 - R15 are available in
ARM-mode (usr, user)
• R0 - R12 are general purpose registers
• R13 is Stack Pointer (SP)
• R14 is subroutine Link Register
• Holds the value of R15 when BL-instruction is executed
• R15 is Program Counter (PC)
• Bits 1 and 0 are zeroes in ARM-state (32-bit addressing)
• R16 is state register (CPSR,Current Program Status Regist


download full report
tisu.it.jyu.fi/embedded/TIE345/luentokalvot/Embedded_3_ARM.pdf
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24-02-2011, 02:55 PM


.ppt   02_ARM_Architecture.ppt (Size: 1.58 MB / Downloads: 51)
The ARM Architecture
 Founded in November 1990
 Spun out of Acorn Computers
 Designs the ARM range of RISC processor cores
 Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.
 ARM does not fabricate silicon itself
 Also develop technologies to assist with the design-in of the ARM architecture
 Software tools, boards, debug hardware, application software, bus architectures, peripherals etc
Intellectual Property
 ARM provides hard and soft views to licencees
 RTL and synthesis flows
 GDSII layout
 Licencees have the right to use hard or soft views of the IP
 soft views include gate level netlists
 hard views are DSMs
 OEMs must use hard views
 to protect ARM IP
Data Sizes and Instruction Sets
 The ARM is a 32-bit architecture.
 When used in relation to the ARM:
 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)
 Most ARM’s implement two instruction sets
 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set
 Jazelle cores can also execute Java bytecode
Processor Modes
 The ARM has seven basic operating modes:
 User : unprivileged mode under which most tasks run
 FIQ : entered when a high priority (fast) interrupt is raised
 IRQ : entered when a low priority (normal) interrupt is raised
 Supervisor : entered on reset and when a Software Interrupt
instruction is executed
 Abort : used to handle memory access violations
 Undef : used to handle undefined instructions
 System : privileged mode using the same registers as user mode
The Registers
 ARM has 37 registers all of which are 32-bits long.
 1 dedicated program counter
 1 dedicated current program status register
 5 dedicated saved program status registers
 30 general purpose registers
 The current processor mode governs which of several banks is accessible. Each mode can access
 a particular set of r0-r12 registers
 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr
Privileged modes (except System) can also access
 a particular spsr (saved program status register)
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karabi borah
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#3
24-09-2011, 09:45 PM

i want a seminar and presentation report on arm architecture
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26-09-2011, 02:24 PM


to get more information about the topic " ARM architecture" please refer the link bellow

topicideashow-to-arm-architecture?pid=56886#pid56886
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