CELL
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31-01-2009, 11:16 AM


Cell is the code name given for a super computer on a chip. Protagonists of this new cell architecture are IBM, Sony and Toshiba. They have invested more than US$400 million for the complete research project and implimentation which is spread over a period of five years. The development center is situated at Austin, Texas, USA, which is staffed with nearly 300 skilled computer architects, engineers & chip designers. While much of the work on cell is complete, there?s still a lot of work is left to do. Together the hardware & software teams will continue testing the chip?s inner workings. The last stage of development work which still lies a head, includes completing circuit layout and then eventually testing actual sample chips. On completion it is expected to replace the existing processors widely due to its earlier mentioned features and thus also boost the upcoming broad band network technology. It is also supposed to boost the performance of the existing electronic devices. Thus it will open a platform for new era of devices
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29-06-2010, 12:23 AM

CELL
Abstract
Abstract Cell is the code name given for a a chip. It is a multicore CPU under development by a joint venture between Sony, Toshiba, and IBM (STI). Sony has confirmed that the Cell processor will power their Playstation 3 video game console. On completion it is expected to replace the existing processors widely due to its earlier mentioned features and thus also boost the upcoming broadband network technology. It is also supposed to boost the performance of the existing electronic devices. Thus it will open a platform for new era of devices. Technical details for the Cell have not yet been released, but informed speculation indicates that one cell chip will do 1 trillion floating point operations per second, 1 TFLOP. This speed is several hundred times faster than a high-end personal computer. The fundamental idea of the CELL processor project and implimentation is to give up the pursuit of single threaded performance, in favour of allocating additional hardware resources to perform parallel computations. That is, minimal resources are devoted toward the execution of single threaded workloads, so that multiple DSP-like processing elements can be added to perform more parallelizable multimedia-type computations
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