CMOS TIME INTERLEAVED ADC full report
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21-05-2010, 07:48 PM
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A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b “backend” folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter
input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18- m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.
CMOS Nyquist-rate analog-to-digital converters (ADCs) in modern electronic systems tend to fall in two broad categories: those that operate at very high sampling rates, up to several gigahertz, with resolution in the range of 4–8 b, and those that perform conversions at rates of tens of megahertz while providing resolution in the range of 10–15 b. The very high-speed low-resolution converters find use primarily in applications such as instrumentation, wideband communications, and data retrieval from magnetic storage media. Power consumption is rarely a primary concern in these applications, and the principal challenge is to achieve a high sampling rate for resolutions that can be readily achieved within the matching limitations of CMOS technologies. The target applications for converters providing higher resolution at sampling rates of tens of megahertz include communication and medical systems, as well as image and video data acquisition. The challenge here is to achieve a high resolution in the presence of component mismatch, thermal noise, and circuit nonlinearity.
The ADC introduced in this work targets performance between the two categories noted above, namely, a sampling rate of 150 MSample/s and a resolution of 8 bits. These specifications are typically appropriate for high-speed wireline and wireless communications. For example, the 1000BASE-T Ethernet protocol requires a conversion rate of 125 MSample/s and a resolution of 7–9 bits, depending on the overall system architecture. Since four converters must be integrated in a single transceiver, power consumption becomes an important consideration. For the IEEE 802.11a/g wireless LAN protocol, ADCs with conversion rates of the order of 80 MSample/s are required, also with resolution in the range of 7–9 bits. Here, power consumption is of paramount importance when the target application is portable systems.
The low-power ADC described in this paper utilizes a combination of architectural concepts and circuit techniques to achieve the target performance while dissipating only 71 mW of power from a 1.8-V supply. Chapter II provides a detailed overview of the converter architecture and reviews the choices made to minimize the power dissipation. Chapter III describes the design of the circuit blocks that have been used to accommodate low-voltage operation. Chapter IV presents measured results for the experimental prototype.
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