CMOS VLSI Design
Active In SP
Joined: Sep 2010
14-10-2010, 10:35 AM
cmos_vlsi_design_ldce.ppt (Size: 183.5 KB / Downloads: 144)
Plenty of Room at the bottom??
Currently at 45 nm process node and soon to be on 28 nm
Lithography was seen to be a major obstacle (dealt with using Immersion or X/EUV)
Moore’s Law still holding but for how long?
Transistors on die doubling and so is the Fab cost (Standing at close to 5bn for latest tech)
STI (Shallow Trench Isolation), CMP (Chemical Mechanical Polishing) and other process enhancements are now part of all manufacturing
Cu Interconnects replacing Al
Low-K dielectric for successive metalization
High-K Oxide for the Gate
Metal Gate replacing Polysilicon
Active In SP
Joined: Feb 2012
31-03-2012, 09:39 AM
to get information about the topic "cmos designs in vlsi" full report ppt and related topic refer the link bellow
seminar and presentationproject and implimentationsshowthread.php?tid=14574&google_seo=WEy2++++++++++++++++++++&pid=27265
Joined: Apr 2012
15-06-2012, 12:51 PM
CMOS VLSI Design
CMOS VLSI Design.doc (Size: 72.5 KB / Downloads: 37)
Lab 5 Microprocessor Assembly
1. Top-Level Schematic Simulation
Copy your lab4_xx library to lab5_xx for this lab. Look at the top-level mips cell that includes your datapath, alucontrol, and controller icons. The system has the exported inputs and outputs given in Table 1. Notice that the internal wires and icons are also named to simplify debugging.
2. Top-Level Layout
Create a new layout in the lab5_xx library named mips. In this top-level cell, place your datapath, alucontrol, and controller so that they will be easy to connect. Wire together the modules. Don’t forget to connect power and ground with fat wires and arrays of vias to handle the higher levels of current that may flow! You will avoid creating a rats nest of wiring if you systematically reserve metal2 for vertical lines and metal1 for horizontal lines. You may wish to consider placing a large number of long horizontal wires between the datapath and the controller/alucontrol, then dropping vertical lines in a systematic fashion to connect the blocks together.
3. Pad Frame Assembly
The tiny transistors on a chip must eventually be attached to the external world with a pad frame. A pad frame consists of metal pads about 100 microns square; these pads are large enough to be attached to the package during manufacturing with thin gold bonding wires. Each pad also contains large transistors to drive the relatively enormous capacitances of the external environment.
The final step in designing a chip is creating a file containing the geometry needed by the vendor to manufacture masks. Once upon a time these files were written to magnetic tape, and the process is still known as tapeout. The two popular output formats are CIF and GDS; we will use CIF (the Caltech Interchange Format) because it is a human-readable text file and thus easier to inspect for problems than the binary GDS format. To write a CIF file.
If you have successfully completed the lab, congratulations! You have designed, assembled, and tested your own microprocessor! You now are familiar with the major aspects of custom CMOS VLSI design.