Capacitor Balance Issues of the Diode-Clamped Multilevel Inverter Operated in a Quasi
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20-10-2010, 10:36 AM




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ABSTRACT

A new operational mode for diode-clamped multilevel inverters termed quasi two-level operation is proposed. Such operation aims to avoid the imbalance problem of the dc-link capacitors for multilevel inverters with more than three levels and reduces the dc-link capacitance without introducing any significant voltage ripple at the dc-link nodes. The proposed operation can be generalized for any number of levels. The validity of the proposed multilevel inverter operational mode is confirmed by simulations in mat lab v7.5. .
The multilevel concept is based on a step approximation to a sinusoidal voltage. Multilevel inverters belong to the inverter circuit family, where the output voltage comprised more than two intermediate discrete voltage levels. The purpose of these circuits is to generate a high-voltage waveform using lower voltage rating switching devices connected in series. Typically, the series-connected devices are sequentially switched, producing an output pattern that contains discrete predefined steps. Each switch blocks its rated normal voltage, but the total output voltage can be much higher. Multilevel inverters, in general, have advantages over conventional two level inverters due to their ability to handle high voltage with minimum voltage stress on the switching devices, have a low harmonic content in the output voltage, generate lower dv/dt, and have a lower common-mode voltage, which results in reduced stress on motor bearings in drive applications. In diode-clamped multilevel inverters, device voltage sharing is achieved via the clamping diodes, whereas lower dv/dt is achieved with stepped voltage changes. However, the diode clamped multilevel suffers from dc-link capacitor unbalance to balance the dc-link series capacitors, two main balancing approaches have been proposed: 1) the use of auxiliary balancing networks and 2) the manipulation of redundant switch states.


OVERVIEW OF THE PROJECT
SERIES connection of semiconductor devices is a solution for achieving higher converter voltage ratings; however, devices suffer from unbalanced static and dynamic voltage sharing, and the output voltage has a high dv/dt. A multilevel inverter can overcome these disadvantages. The multilevel concept is based on a step approximation to a sinusoidal voltage. Multilevel inverters belong to the inverter circuit family, where the output voltage comprised more than two intermediate discrete voltage levels. The purpose of these circuits is to generate a high-voltage waveform using lower voltage rating switching devices connected in series. Typically, the series-connected devices are sequentially switched, producing an output pattern that contains discrete predefined steps. Each switch blocks its rated normal voltage, but the total output voltage can be much higher. Multilevel inverters, in general, have advantages over conventional two level inverters due to their ability to handle high voltage with minimum voltage stress on the switching devices, have a low harmonic content in the output voltage, generate lower dv/dt, and have a lower common-mode voltage, which results in reduced stress on motor bearings in drive applications. In diode-clamped multilevel inverters, device voltage sharing is achieved via the clamping diodes; where as lower dv/dt is achieved with stepped voltage changes. However, the diode clamped multilevel suffers from dc-link capacitor unbalance to balance the dc-link series capacitors, two main balancing approaches have been proposed: 1) the use of auxiliary balancing networks and 2) the manipulation of redundant switch states. Auxiliary networks achieve capacitor balance by the transfer of energy between the capacitors or the direct transfer of energy from the link supply.
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