Cellular Neural Network
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Computer Science Clay
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25-02-2009, 12:26 AM


Cellular Neural Network

Cellular Neural Network is a revolutionary concept and an experimentally proven new computing paradigm for analog computers. Looking at the technological advancement in the last 50 years ; we see the first revolution which led to pc industry in 1980's, second revolution led to internet industry in 1990's cheap sensors & mems arrays in desired forms of artificial eyes, nose, ears etc. this third revolution owes due to C.N.N.This technology is implemented using CNN-UM and is also used in imageprocessing.It can also implement any Boolean functions.

ARCHITECTURE OF CNN

A standard CNN architecture consists of an m*n rectangular array of cells c(i,j) with Cartesian coordinates (i,j) i=1,2¦..M, j=12¦...N.

A class -1 m*n standard CNN is defined by a m*n rectangular array of cells cij located at site (i,j) i= 1,2 ¦¦.m ,j=1,2,¦.n is defined mathematically by
(dXij/dt )= -Xij + A(I,j,k,l) Ykl + B(i,j,k,l) + Zij
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mangalsitm
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20-11-2010, 12:43 PM

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22-11-2010, 10:16 AM

hi mangalsitm,
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02-05-2012, 04:02 PM

Cellular Neural Network



.docx   INTRODUCTION CNN.docx (Size: 393.1 KB / Downloads: 30)


INTRODUCTION

Cellular Neural Network is a revolutionary concept and an experimentally proven new computing paradigm for analog computers. Cellular neural networks (CNN) are a parallel computing paradigm similar to neural networks, with the difference that communication is allowed between neighbouring units only. Typical applications include image processing, analyzing 3D surfaces, solving partial differential equations, reducing non-visual problems to geometric maps, modeling biological vision and other sensory-motor organs. Looking at the technological advancement in the last 50 years ; we see the first revolution which led to pc industry in 1980’s, second revolution led to internet industry in 1990’s cheap sensors & mems arrays in desired forms of artificial eyes, nose, ears etc. this third revolution owes due to C.N.N.
This technology is implemented using CNN-UM and is also used in image processing. It can also implement any Boolean functions.


DIGITAL HARDWARE ACCELERATORS

We can emulate analog dynamics by digital hardware accelerators. Emulating large CNN arrays need more computing power. A special hardware accelerator board (HAB) was developed for simulating up to one million pixel arrays with on board memory, with 4 DSP chips. Using hab’s large arrays can be simulated with cheap pc. Actually the DSP is a reduced instruction set (RISC). Processor used for calculating CNN dynamics. New dsp packages host 4-8 dsp processors in a chip .hence the process numbers are 4-8 times higher .since for the calculation of CNN dynamics ,a major part of dsp is not used , a special purpose chip (castle) have been developed



SIMPLICAL CNN

Recently a novel structure has been introduced to implement any Boolean / gray level function of any number of variables .The output is no longer restricted to be binary so that CNNs with gray scale outputs are obtained. Simplical CNNs are implemented using RTDs (resonant tunneling diodes)
RTDs are nano electric quantum device is featuring high speed regims and small integration sizes and they can be designed to operate in nano /femto sizes leading to extreme low power designs. In addition they exhibit an intrinsic non linear behaviour which can be exploited in many diverse applications, for instance in frequency multiplier and parity generators the threshold logic gates multi gigahertz a-d converters, and multivalued logic applications including multivalued memory design among others.


IMPLEMENTATION OF SIMPLICAL R.T.D. C.N.N.

The first block is responsible for vertex code generation, whereas the second block is responsible for producing the values of function at the vertices . Finally there is the interpolation state, which is the charge of producing the result

VERTEX CODE GENERATOR

The vertex code generator is the part of the circuit that receives as input the nine values {u1, u2, …u9}. Corresponding to the inputs associated with central pixel and its 8 neighbours & generates s a code. This code is used to retrieve the value of associated parameter. The key component of vertex code generator is a comparator. One way to implement this is using a single R.T.D in current mode configuration as in the circuit illustrated below.



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