Design For Testability
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#1
28-06-2010, 11:41 PM


Design For Testability

Abstract
IC manufacturing process is inherently very defective. Only about 20 percent of manufactured ICs are good. But there is requirement for high quality ICs. Being able to design a workable system solution for a given problem is only half the battle .We must also be able to test the system to a degree which ensures that we can have a high confidence level that it is fully functional. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could adversely affect the productâ„¢s correct functioning. The defects are converted to fault models and appropriate patterns are used to detect faults. Design for Testability or DFT is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to make ATPG easier. There are different types of DFT known as Ad-Hoc and Structural. Structural DFT is further classified as Scan Methods and Built in Self test. Different methods are applied according to the need and type of design. The DFT techniques applied in digital circuits are discussed. They have an effect on the cost and security of the manufactured ICs. Different test tools are being developed to make testing an easier process. DFT techniques have become an integral part of IC design due to miniaturization and ever increasing number of gates in a chip.
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#2
25-04-2012, 05:11 PM

Design For Testability



.pdf   DFTnew.pdf (Size: 324.91 KB / Downloads: 89)

Testability

• Controllability: The ability to set some
circuit nodes to a certain states or logic
values.
• Observability: The ability to observe the
state or logic values of internal nodes.


Usage of Testability Measures

• Speed up test generation
• Improve the design testability
• Guide the DFT insertion


SCOAP

• Sandia Controllability Observability Analysis
Program.
• Using integers to reflect the difficulty of controlling
and observing the internal nodes.
• Higher numbers indicate more difficult to control or
observe.
• Applicable to both combinational & sequential
circuits.


Costs Associated with DFTs

• Pin Overhead
• Area / Yield
• Performance degradation
• Design Time
⇒There is no free lunch !


Flip-Flop Selection Algorithm


• Identify all cycles
• Repeat
for each vertex
count the frequency of appearance in the cycle list
select the most frequently used vertex
remove all cycles containing the remove (selected) vertex
until (cycle list is empty)
! This is a feedback vertex set problem, a wellknown
NP-complete problem, hence heuristic is
used.
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