Dynamic Logic Circuits
project report helper Active In SP Posts: 2,270 Joined: Sep 2010 
01102010, 11:02 AM
dynamic cmos.ppt (Size: 895.5 KB / Downloads: 92) Dynamic Logic Circuits abstract Dynamic logic is temporary (transient) in that output levels will remain valid only for a certain period of time Static logic retains its output level as long as power is applied Dynamic logic is normally done with charging and selectively discharging capacitance (i.e. capacitive circuit nodes) Precharge clock to charge the capacitance Evaluate clock to discharge the capacitance depending on condition of logic inputs Advantages over static logic: Avoids duplicating logic twice as both Ntree and Ptree, as in standard CMOS Typically can be used in very high performance applications Very simple sequential memory circuits; amenable to synchronous logic High density achievable Consumes less power (in some cases) Disadvantages compared to static logic: Problems with clock synchronization and timing Design is more difficult 


seminar ideas Super Moderator Posts: 10,003 Joined: Apr 2012 
23042012, 01:08 PM
Dynamic Logic Circuits chapter5_ckts_C.ppt (Size: 795.5 KB / Downloads: 23) Dynamic logic is temporary (transient) in that output levels will remain valid only for a certain period of time Static logic retains its output level as long as power is applied Dynamic logic is normally done with charging and selectively discharging capacitance (i.e. capacitive circuit nodes) Precharge clock to charge the capacitance Evaluate clock to discharge the capacitance depending on condition of logic inputs Advantages over static logic: Avoids duplicating logic twice as both Ntree and Ptree, as in standard CMOS Typically can be used in very high performance applications Very simple sequential memory circuits; amenable to synchronous logic High density achievable Consumes less power (in some cases) Disadvantages compared to static logic: Problems with clock synchronization and timing Design is more difficult NMOS Dynamic Logic Basic Circuit The basic dynamic logic gate concept is shown at left (top) the pass transistor MP is an NMOS device, but could also be implemented with a transmission gate TG Cx represents the equivalent capacitance of the input gate of the second NMOS device (part of an inverter or logic gate) as well as the PN junction capacitance of MP’s drain (source) When clock CK goes high, MP is turned on and allows the input voltage Vin to be placed on capacitor Cx Vin could be a high (“1”) or a low (“0”) voltage When CK goes low, MP is turned off, trapping the charge on Cx Operation for a 1 or a 0: If Vin is high (say VOH), then MP will allow current to flow into Cx, charging it up to Vdd – Vtn (assume CK up level is Vdd) If Vin is low (say GND), then MP will allow current to flow out of Cx, discharging it to GND Due to leakage from the drain (source) of MP, Cx can only retain the charge Q for a given period of time (called soft node) If MP is NMOS, Cx will discharge to GND If MP is PMOS, Cx will discharge to VDD If MP is a TG, Cx could discharge in either direction Leakage and Subthreshold Current in Dynamic Pass Gate Charge can leak off the storage capacitor Cx mainly from two sources: PN junction leakage of the NMOS drain (source) junction Subthreshold current (IOFF) through MP when its gate is down at zero volts One can solve for the maximum amount of time t that charge can be retained on Cx using the differential equation C dv/dt = I, where I is the total of the reverse PN junction leakage and the IOFF current C is the total load capacitance due to gate, junction, wire, and poly capacitance the maximum allowable V in order to preserve the logic “1” level is known Typically V ~ Vdd – Vtn – ½ Vdd = ½ Vdd – Vtn The minimum frequency of operation can be found from f ~ 1/(2 t) Mixing Domino CMOS Logic with Static CMOS Logic We can add an even number of static CMOS inverting logic gates after a Domino logic stage prior to the next Domino logic stage Even number of inverting stages guarantees that inputs to the second Domino logic stage experience only 0to1 transitions (since 1to0 transitions may cause an erroneous logic level as discussed in prior charts 567 and 568) In the cascaded Domino logic structure, the evaluation of each stage ripples through the cascaded stages similar to a chain of Dominos (from which it takes the name) The evaluate cycle must be of sufficient duration to allow all cascaded logic stages (between latches) to complete their evaluation process within the clock evaluation interval Low Voltage Swing GTL I/O Design Low voltage swing drivers are often needed to drive bipolar ECL inputs or to reduce dynamic power on I/O buses GTL driver (Gunning Transistor Logic) uses opendrain N pulldown output devices with 50 ohm terminating resistors connected to VT (1.2 volts) to drive chiptochip interconnections Allows limited swing (0.8 volt) chiptochip buses to reduce ac power Similar to bipolar open collector driver scheme used in ECL logic Driver ckt (b) includes devices N2 & N3 plus INV1 & INV2 to reduce di/dt and limit overshoot reflections Down level VOL is 0.4 volt due to dc ratio with 50 ohm pull up resistor Reduced swing input receiver © is a differential amplifier swinging +/ 0.4 volt around Vref = 0.8 volt 


