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29-12-2010, 10:56 AM

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DIMS is the approach usually taken to create QDI circuits. It allows logic to be constructed without the need for matched delays. Unfortunately DIMS gates are large, slow and power-hungry as shown in figure 3.1, due to the C-elements which are required to ensure that the output only rises when all inputs are valid and fall only when they return to NULL.

A DIMS gate has the following properties:
1) Outputs NULL when all inputs are NULL.
2) Executes the required logical operation.
3) Only outputs a valid value when all inputs are valid.
4) Only returns to NULL when all inputs are NULL.
The early output has properties 1 and 2 only, so some other mechanism must be provided to ensure correct operation.

Property 3 ensures that only when all inputs into a stage are valid, then the result will become valid. In an early output logic system, this is undesirable, as early output logic generates results as soon as sufficient inputs have arrived to determine the output. Here, the requirement is that all the inputs must have been asserted before they can be acknowledged. Figure 3.2 shows an example of an early output pipeline stage. Here, Ri, Ro are the request signals; Ai, Ao are the acknowledge signals; Vo is the Valid signal. Two levels of C-element are used to guarantee operation. The first C-elements (C1 and C2) are adjacent to the output latches; these ‘guarding’ C-elements produce an acknowledge when the output latches have captured the input data – the timing of which is implicit in the (black) data signals – and all the contributing input stages have output valid data. These then signal an acknowledgement to the input latches. This ensures that a latch will not receive an acknowledge until it is ready and rises its output data.

The second set of C-elements ensures that in all the latches, the data has been sent to have acknowledged before the input latch may change. These C-elements also ensure that all relevant latches achieve a NULL state in between data values. This mechanism requires a ‘valid’ (Vo) signal to accompany the data assertion. In a four-phase, dual-rail system this may simply be provided by an OR of the input bits.

Logic gates such as AND and OR have a 50% probability of generating a result with only one of their inputs present.
The structure of a two input early output OR gate (Charles Brej, 2005) is demonstrated in figure3.3. The OR gate generates an early output when either of two inputs are 1. To complete the set of input states the AND gate generates an output when both inputs are valid but they are not covered by the early output set (both are 0).

This combination can be used to create any dual-rail early output AND/OR gate with or without inversions on inputs and outputs.

The AND/OR gates output one value when all inputs are in a particular state and output the other value in all other input combinations. Any inversions of inputs or outputs can be performed by swapping the wires representing 1 and 0.


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