HIGH SPEED/LOW POWER MULTIPLIER WITH THE SPURIOUS POWER SUPPRESSION TECHNIQUE
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Electrical Fan
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#1
09-12-2009, 02:42 PM



.ppt   HIGH SPEEDLOW POWER MULTIPLIER WITH THE SPURIOUS POWER SUPPRESSION TECHNIQUE.ppt (Size: 491 KB / Downloads: 321)
Abstract:

This project and implimentation provides the experience of applying an advanced version of Spurious Power Suppression Technique (SPST) on multipliers for high speed and low power purposes. When a portion of data does not affect the final computing results, the data controlling circuits of SPST latch this portion to avoid useless data transition occurring inside the arithmetic units, so that the useless spurious signals of arithmetic units are filter out. Modified Booth Algorithm is used in this project and implimentation for multiplication which reduces the number of partial product to n/2.
To filter out the useless switching power, there are two approaches, i.e using registers and using AND gates, to assert the data signals of multipliers after data transition. The simulation result shows that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a significant speed improvement and power reduction

SPURIOUS POWER SUPPRESSION TECHNIQUE


The SPST uses a detection logic circuit to detect the effective data range of arithmetic units, e.g. adders, or multipliers.

The proposed technique adopts the design concept of separating the arithmetic units into Most Significant Part (MSP) and Least Significant Part (LSP), and then freezing the MSP whenever this part of circuits does no affect the computation result.

There is a data asserting control realized by using registers or AND to further filter out the useless spurious signals of the arithmetic units every time when the latched portion is turned on.
Use Search at http://topicideas.net/search.php wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion
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v.uma maheswari
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#2
14-10-2010, 11:21 PM

Im pursuing final year ME VLSI DESIGN. My project and implimentation is spurious power supression technique for multimedia applications. Im need of verilog coding for spst adder/subtractor circuit.
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seminar flower
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18-07-2012, 10:14 AM

HIGH SPEED/LOW POWER MULTIPLIER WITH THE SPURIOUS POWER SUPPRESSION TECHNIQUE


.pptx   HIGH SPEEDLOW POWER MULTIPLIER.pptx (Size: 472.13 KB / Downloads: 39)

INTRODUCTION

Why emphasize low power consumption
Longer battery life for mobile devices.
Increases reliability by reducing switching current.
Results in lower heat dissipation.
Low heat dissipation can reduce packaging cost.
Major resources for power dissipation in digital CMOS circuits are
Switching power
Short circuit power
Leakage power
Switching activity at capacitance nodes is a major source of power dissipation and the switching power is
pswitching= αCvdd² fclk
where
α=Switching activity
C=Loading capacitance
vdd=supply voltage
fclk=operating frequency

Adder/subtractor circuit:

The 16-bit adder/subtractor is divided into MSP and LSP at the place between the 8th bit and the 9th bit.
Latches implemented by simple AND gates are used to control the input data of the MSP.

DETECTION LOGIC CIRCUIT

When the MSP is turned on, the input data remain the same as usual, while the MSP is turned off, the input data become zero values to avoid glitching power consumption.
The data are separated into the Most Significant
Part (MSP) and the Least Significant Part (LSP).

APPLICATION:

Important design challenges of wireless multimedia and digital signal processor (DSP) applications.
Accuracy in measuring gold(carat-wise).
Calculation of range in radar systems.
Used in Chemical Industries.





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