High-Throughput Low-Cost AES Processor
Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
project report helper
Active In SP

Posts: 2,270
Joined: Sep 2010
20-10-2010, 10:54 AM

.pdf   aes algorithm1.pdf (Size: 105.48 KB / Downloads: 85)
High-Throughput Low-Cost AES Processor

Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, and Cheng-Wen Wu, National Tsing Hua University


We propose an efficient hardware implementation of the Advanced Encryption Standard algorithm, with key expansion capability. Compared to the widely used table lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-Box by 64 percent. Our pipelined design has a very high throughput rate. Using typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate in the non-feedback cipher mode is 2.38 Gb/s for 128-bit keys, 2.008 Gb/s for 192-bit keys, and 1.74 Gb/s for 256-bit keys, respectively. Testability of the design is also considered. The hardware cost of the AES design is approximately 58K gates using a standard synthesis flow.


The rapidly growing number of Internet and wireless communication users has led to increasing demand for security measures and devices to protect user data transmitted over open channels. Two types of cryptographic systems have been developed for that purpose: symmetric (secret key) and asymmetric (public key) cryptosystems. Symmetric cryptography, such as in the Data Encryption Standard (DES), 3DES, and Advanced Encryption Standard (AES) [1], uses an identical key for the sender and receiver, both to encrypt the message text and decrypt the cipher text. Asymmetric cryptography, such as in the Rivest-Shamir-Adleman (RSA) and Elliptic Curve algorithms, uses different keys for encryption and decryption, eliminating the key transportation dilemma. Symmetric cryptography is more suitable for the encryption of a large amount of data. The AES algorithm defined by the National Institute of Standards and Technology (NIST) of the United States has been widely accepted to replace DES as the new symmetric encryption algorithm [1]. AES encryption is an efficient scheme for both hardware and software implementation. Much work has been presented on hardware implementations of AES using field programmable gate arrays (FPGAs) [2–5], and comprehensive analyses of the performance of the AES finalists was presented based on FPGA implementations, before Rijndael was selected as the AES algorithm. Mostapproaches use a ROM/RAM-based lookup table (LUT) to implement the most critical transformation step in the AES algorithm, the SubBytes transformation (also known as the S-Box). This approach is cost effective for SRAM-based FPGAs, but may not be a good choice for application- specific integrated circuit (ASIC) implementation. An alternative LUT-based approach that combines the S-Box and MixColumn transformation has been reported using different technologies [6, 7]. Besides the LUT-based approaches, results from several other project and implimentations have shown that implementing an arithmetic circuit in a composite field to compute the multiplicative inverse and affine transformation of the S-Box provides an excellent trade-off between silicon area and performance. The composite field implementation was first recommended by the inventor of Rijndael [8]. Some implementations based on this idea can be found in [9–12]. An extended low-power implementation was proposed in [13], and in [14] a unified hardware architecture where the AES and Camellia algorithms share the same composite-field inverse function was also presented. We present a hardware-efficient design for the AES algorithm. The S-Box was implemented based on composite-field arithmetic [11]. The chip has been implemented and verified for both encryption and decryption, with standard key lengths of 128, 192, and 256 bits. The key expansion procedure was also implemented on the chip.

Important Note..!

If you are not satisfied with above reply ,..Please


So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page

Quick Reply
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  high speed electronics devices ppt jaseelati 0 292 23-01-2015, 02:18 PM
Last Post: jaseelati
  high voltage fuse blown indicator with voice based announcement system jaseelati 0 336 15-01-2015, 03:58 PM
Last Post: jaseelati
  stability of high rise buildings ppt jaseelati 0 239 07-01-2015, 03:47 PM
Last Post: jaseelati
  high speed electronics devices ppt jaseelati 0 274 07-01-2015, 02:31 PM
Last Post: jaseelati
  low power and area efficient carry select adder ppt padmajaece405 1 426 15-10-2014, 03:02 PM
Last Post: mkaasees
Last Post: Guest
  ARM Processor Instruction Set pdf study tips 0 375 02-09-2013, 04:25 PM
Last Post: study tips
  Low Cost Toll Audit System to Maximize Toll Revenues study tips 0 296 17-08-2013, 04:30 PM
Last Post: study tips
  Basic Processor Architecture of 8085(µp) study tips 0 445 10-08-2013, 04:56 PM
Last Post: study tips
  Two-Stage Enhancement for Low Quality Fingerprint Images in Spatial Report study tips 0 361 22-06-2013, 03:36 PM
Last Post: study tips