INTER INTEGRATED CIRCUIT BUS CONTROLLER
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Joined: Dec 2008
17-09-2009, 01:56 AM
INTER INTEGRATED CIRCUIT BUS CONTROLLER
The I2C stands for Inter Integrated circuit helps in establishing short distance communication between ICs. The communication takes place in accordance with the Philips I2C bus protocol.
In todayâ„¢s highly complex circuits, I2C plays a major role in reducing the interconnection complexity between the ICs.
I2C bus is a 2 wire bi-directional serial bus. One wire is for data transmission named as Serial data bus (SDA) and the other for clock signal transmission (SCL). These carry information between the devices connected to the bus.
I2C is easy to use to link multiple devices together since it has built in addressing scheme.
Our project and implimentation aim involves the design of both master and slave cores. The master core is responsible for initiating the communication on the bus. The slave core is the device that has been addressed by the master in order to establish effective communication. Each slave has a unique address and responds only after it has verified the address sent by the master. I2C is a true multi master bus; this means that more than one master can attempt to control the bus at the same time without corrupting the message. This is achieved by a technique known as arbitration, where if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted.
Another concept known as clock synchronization is used in order to synchronize clock signals of two or more devices. It is performed using the wired-AND connection of I2C interface to SCL line. Devices with shorter LOW periods enter a HIGH wait-state during this time.
The RTL code for the design has been done using Verilog HDL. The functional verification has been done using ModelSim and the code has been synthesized using Xilinx ISE. This has been finally implemented onto a FPGA Spartan IIE kit.
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16-04-2010, 02:08 PM
hi plz read dis jagas
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20-04-2010, 06:27 AM
nice work INTER INTEGRATED CIRCUIT BUS CONTROLLER
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02-05-2011, 12:10 PM
Miss. Pooja P. Warhekar
INTER INTEGARTED CIRCUIT.pptx (Size: 423.46 KB / Downloads: 63)
INTER INTEGARTED CIRCUIT PROTOCOL
Serial communication protocols
Meant for short distances “inside the box”
Low speed ( a few Mbps at the fastest )
What is I2C
Shorthand for an “Inter-integrated circuit” bus
I2C compatible devices include EEPROMs, thermal sensors, and real-time clocks (more than 150)
Used as a control interface to signal processing devices that have separate data interfaces, e.g. RF tuners, video decoders and encoders, and audio processors.
I2C bus has three speeds:
Slow (under 100 Kbps)
Fast (400 Kbps)
High-speed (3.4 Mbps) – I2C v.2.0
Limited to about 10 feet for moderate speeds
I2C Bus Configuration
It was developed by Philip’s semiconductor in 1980’s.
To provide an easy way to connect a CPU to its periferral chips in a TV-set.
Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)
Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers
It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer
Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the standard mode or up to 400 kbit/s in the fast mode
The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF.
Features from desiner point of view
Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic
No need to design bus interfaces because the I2C-bus interface is already integrated on-chip
Integrated addressing and data-transfer protocol allow systems to be completely software-defined
The same IC types can often be used in many different applications
Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs
ICs can be added to or removed from a system without affecting any other circuits on the bus
Fault diagnosis and debugging are simple; malfunctions can be immediately traced
1. Master sends start condition (S) and controls the clock signal
2. Master sends a unique 7-bit slave device address
3. Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit
4. Receiver sends acknowledge bit (ACK)
5. Transmitter (slave or master) transmits 1 byte of data
6. Receiver issues an ACK bit for the byte received
7. Repeat 5 and 6 if more bytes need to be transmitted.
8.a) For write transaction (master transmitting), master issues stop condition (P) after last byte of data.
8.b) For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
Start – high-to-low transition of the SDA line while SCL line is high
Stop – low-to-high transition of the SDA line while SCL line is high
Ack – receiver pulls SDA low while transmitter allows it to float high
Data – transition takes place while SCL is slow, valid while SCL is high
I2c Bus Hardware
0pen drain or open collector outputs(Depending on technology)
When bus is IDLE, bus lines are at logic HIGH state
Wired AND logic
Built in bus-mastering technique
Serious effect on speed due to open collector configuration
As length increases RC time constant increases
I2c Bus Arbitration
A master which transmits a HIGH level when other is transmitting a LOW will loose arbitration
Address as well as data signals are used for arbitration
Risk of data curruption
No risk of data corruption.
Data valid in high period of clock
Use of wired AND connection for clock synchronisation
LOW period determined by the device with the longest clock LOW
HIGH period determined by the device with the SHORTEST clock HIGH
Good for communication with on-board devices that are accessed occasionally.
Easy to link multiple devices because of addressing scheme
Cost and complexity do not scale up with the number of devices
Assignment of slave addresses.
Supports a limited range of speed.