Localized Charge Storage in Nanocrystal Memory Cells
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28-10-2010, 07:33 AM


Localized Charge Storage in Nanocrystal Memory Cells
Presented by:-
Naveen N R
S-7 AEI
College Of Engineering, Trivandrum
2007-11 batch



.pptx   Localized Charge Storage in Nanocrystal Memory Cells.pptx (Size: 410.26 KB / Downloads: 58)
Hi guys, If you like this presentation, say hi to naveen at :maxpayne1989@gmail.com

Overview
Memory Classification
Floating Gate MOSFET
Structure & Working
Limitations
Nanocrystal Memory
Fabrication
Programming & Erasing
Characteristics
Advantages
Challenges


Memory Types
Volatile
SRAM
DRAM (SDRAM, DDR RAM)

Non-Volatile
ROM (PROM, EPROM, EEPROM)
Flash Memory (FG-MOSFET)
SONOS
NCM

FG-MOSFET

Electrically isolated floating gate.

Capacitively connected with oxide layer as the dielectric.

Charge stored in the floating gate alters the value of VT.

Acts as a Single memory storage unit.

Using a FG-MOSFET
Charged floating gate indicates a memory value 1.

Cell memory value can be changed to 0 by tunneling.

Tunneling effectively drains the charge stored in the floating gate.
Applications
Memory cards
Flash drives
MP3 players etc.

Limitations
Gate Disturbs.

Drain Disturbs.

High Voltage requirement for write operations.

Long Writing and Erasing times.

Complete loss of charge due to any defect in the oxide layer.

Lateral leakage of charges.

Limited Retentions.

Endurance - Change in threshold values with number of cycles.

Limited scalability due to the use of a thick tunnel oxide.

Capacitive Interference between the Control and Floating Gates.

Nanocrystal Memory

Distributed Charge Storage

Charge stored in randomly distributed and isolated nanocrystals.

Nanocrystals are of size 3-10 nm with a minimum separation of 4 nm between them.

Uses a 5 nm tunnel oxide layer.

Fabrication Techniques

Excess Si - Precipitation

Aerosol Deposition

Direct Growth

Programming an NCM
Use Channel Hot Carrier Injection (CHCI)

Gate supplied with a positive voltage.

Injects channel inversion – layer electrons into the nanocrystals.

Electrons requires a charge greater than nanocrystal conduction band edge.

Erasing an NCM
Use Fowler-Nordheim tunneling.

Gate supplied with a reverse voltage.

Accumulation layer holes tunnel into the nanocrystals from the channel.

Thickness of blocking oxide prevents tunneling between the control gate and the nanocrystals.

Charge Storage in NCM
The threshold voltage shift due to electron storage in the nano crystals is given by
Transfer Characteristics of a Si nanocrystal memory cell before and after Programming.
(available in the ppt)

Coulomb Blockade Effect
Electron addition causes increase in the potential energy of the nanocrystals.

Reduces the electric field and causes a reduction in tunneling current density during writing.

Limits the charge storage capacity of a nanocrystal.

Limits the charge retention capacity.

Limits the use of nanocrystals of size less than 3 nm.

Factors affecting PW
Difference’ is almost zero for cells with no/few NCs.

The amount of charge stored and its uniformity affect the PW and the ‘difference’.

Width of the NCs.

The number and positions of the NCs.

Effect of Charge Stored
Linear and subthreshold PW and ‘difference’ increase linearly with charge stored in NCs.
The Transfer Characteristics of an NCM for different amounts of charge stored.(available in ppt)

Influence of NC Number
Percent ‘Difference’ depends on the uniformity of charge storage.
With a large NC number the charge storage is uniform and ‘difference’ decreases.

Influence of NC Position
PW and Percent ‘Difference’ is highest when the NCs are placed in the central region.
Percent ‘Difference’ is lowest when NCs are placed near the drain region.

Advantages
Immune to oxide defects during program/erase.

Improved Retention.

Reduction in operating voltages.

Improved Scalability.

Simpler fabrication techniques compared to Floating Gate MOSFETs.

Improved Memory Storage Capacity.

Improved Operating Speeds.

Reduced lateral charge flow.

Immune to stress induced leakage current.

Immune to drain induced barrier lowering.

Challenges Ahead
Voltage loss due to poor gate coupling.

Flash devices are proven, mature and trusted with substantial track record of demonstrated reliability.

Flash Memories have started scaling the ETOX cell to 65 nm node.

References
“Effect of Localization of Charges in Nanocrystal Memory Cells”. IEEE Transactions on Electron Devices Vol56, No 10, October 2009.
“Nanocrystal Memory Devices”. IEEE Transactions on Nanotechnology, Vol. 1, No 1, March 2002.
“Silicon nanocrystal non-volatile memory for embedded memory scaling” Microelectronics Reliability 47 (2007).
“Study of data retention of nanocrystal Flash memories”. IEEE International Physics Symposium, April 2003.
“Scaling analysis of phase-change memory technology”. IEEE Non-Volatile Semiconductor Workshop, 2006.
“Characteristics of Si Nano-Crystal Memory”. Journal of Semiconductor Technology and Science, Vol. 1, No 1, March 2001.


.pptx   Localized Charge Storage in Nanocrystal Memory Cells.pptx (Size: 410.26 KB / Downloads: 58)
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