Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
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15-10-2010, 02:59 PM



.ppt   low power high speed hybrid cmos full adder.ppt (Size: 1.08 MB / Downloads: 103)
Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System

Reference Paper:
Chiou-Kou Tung, “A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System,”

Supervisor: Presented By:
Asst. Prof. K.V. Rao Venkatarao Selamneni
MNNIT, Allahabad Reg No.:2009VL18


Introduction

In this paper, a low-power high-speed CMOS
full adder core is proposed.
The five full adders will be compared with the
new proposed full adder.
There are two major methodologies to improve
adder’s performance.

Review

Section review, which reviews the previous
outstanding full adder designs.
These five different types of adders are:
Conventional CMOS full adder
Transmission Function full adder
PTL-based full adder
HPSC full adder
Low-Energy Hybrid full adder
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