Low Power Multiplier Implementation full report
Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
project topics
Active In SP
**

Posts: 2,492
Joined: Mar 2010
#1
02-04-2010, 11:02 AM



.zip   Low Power Multiplier_Radix-3.zip (Size: 113.22 KB / Downloads: 191)
Abstract

There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern VLSI design field. In Very Large Scale Integration, Low power VLSI design is necessary to meet MOOREâ„¢S law and to produce consumer electronics with more back up and less weight. Multiplication occurs frequently in finite impulse response filters, fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia kernels. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. The proposed high speed low power multiplier can attain 30% speed improvement and 22% power reduction in the modified booth encoder when compared with the conventional array multipliers.


Presented By:
C. N.Marimuthu1, P. Thangaraj2,

Read full report
icgstpdcs/Volume8/Issue1/P1170845463.pdf
Use Search at http://topicideas.net/search.php wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion
Reply
jayakuamr
Active In SP
**

Posts: 3
Joined: Jun 2010
#2
17-06-2010, 06:40 PM

i am in need of Low Power Multiplier Implementation full report
Reply
computer science topics
Active In SP
**

Posts: 610
Joined: Jun 2010
#3
18-06-2010, 03:57 PM

do you feel any problem for downloading the attachment and the external link?
Use Search at http://topicideas.net/search.php wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion
Reply
seminars on demand
Active In SP
**

Posts: 201
Joined: Jun 2010
#4
19-06-2010, 07:39 PM

Abstract
A novel reconfigurable low-power high-performance matrix multiplier architecture and its component circuits are described in this article. The processor can be simply reconfigured to calculate the product of matrices X[n,K] and Y[k,m] where n, k, m are integers and b being the precision which ranges from 4 to 64 bits and maximizing the utilization of the hardware available. To illustrate this , the hardware equivalent to one 64×64 bit high precision multiplier can be reconfigured to produce the product of two matrices X8×8 and Y8×8 of 8-bit items in 9 pipeline cycles. The matrix multiplier of size s may consist of an array of (s/m)^2 of m×m. may consist of an array of (s/m)2 of m×m small multipliers utilized in the design.

A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture With Borrow Parallel Counters Counters

The Partial Product Decomposition-Based Arithmetic Architecture:Here the The 4x4 partial product matrix, the addition of the partial product bits, multiplication of two 8-bit numbers using four 4x4 multipliers etc have been shown.Utilizing partial product bit matrix decomposition for full self-testability, Utilizing borrow bits for simple circuit and high speed, more importantly, reducing pass-transistor path length (no more than 4) and rearranging and balancing input bits to each column of small multipliers are done. For more info refer these:

.ppt   A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture.ppt (Size: 307 KB / Downloads: 90)
Use Search at http://topicideas.net/search.php wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion
Reply
seminar paper
Active In SP
**

Posts: 6,455
Joined: Feb 2012
#5
29-02-2012, 09:55 AM

to get information about the topic partial products designing low power multiplier full report ppt and related topic refer the link bellow

topicideashow-to-low-power-multiplier-design-with-row-and-column-bypassing?pid=63776#pid63776

topicideashow-to-design-of-efficient-multiplier-using-vhdl?pid=40971#pid40971

topicideashow-to-low-power-low-area-multiplier-based-on-shift-and-add-architechture

topicideashow-to-low-power-multiplier-implementation-full-report
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page

Quick Reply
Message
Type your reply to this message here.


Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  MULTI-LEVEL INVERTER CAPABLE OF POWER FACTOR CONTROL WITH DC LINK SWITCHES PPT study tips 2 606 06-09-2016, 10:04 AM
Last Post: Dhanabhagya
  IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD (AES) computer science crazy 7 4,780 27-05-2016, 09:18 AM
Last Post: Dhanabhagya
  PHS BASED ONLINE VEHICLE TRACKING SYSTEM full report project topics 6 8,529 07-01-2016, 11:33 AM
Last Post: Guest
  FINGER PRINT BASED ELECTRONIC VOTING MACHINE full report project topics 48 42,498 09-10-2015, 10:18 PM
Last Post: Guest
  RF Based SPY robot full report seminar topics 4 11,789 09-03-2015, 11:25 PM
Last Post: rsnnzxrkv
  vedic multiplier elakkiyaarun 0 293 20-11-2014, 11:00 AM
Last Post: elakkiyaarun
  DIGITAL SPEEDOMETER full report seminar surveyer 8 11,642 30-10-2014, 07:50 PM
Last Post: akhil4718
  MICROCONTROLLER BASED DAM GATE CONTROL SYSTEM full report seminar class 13 10,282 13-07-2014, 11:33 PM
Last Post: Guest
  DOOR LOCKING SECURITY SYSTEM UING GSM FULL REPORT seminar class 11 10,803 14-06-2014, 08:07 PM
Last Post: lagua2012
  REMOTE NOTICE BOARD IMPLEMENTATION USING GSM COMMUNICATION project uploader 2 1,254 09-05-2014, 10:00 AM
Last Post: seminar project topic