Low power and high performance sram design using bank-based selective forward body bi
Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
computer science crazy
Super Moderator

Posts: 3,048
Joined: Dec 2008
21-10-2009, 08:37 PM


Leakage power consumption is large fraction of the total power consumption in contemporary VLSI designs. Since memories occupy a large portion of the total area of many high-performance ICs, it is crucial to reduce the leakage energy of memories. This problem is particularly aggravated for memories implemented in the 45nm technology node, since these processes exhibit significantly higher leakage power. For these memories, leakage is a significant problem not only from a power point of view, but also from performance degradation standpoint. quantify this problem and provide a solution, using a 512KByte SRAM implemented in a 45nm bulk process as a design example. We show that implementing the SRAM as a monolithic memory results in increased delay as well as power. We illustrate a methodology to optimally reduce leakage power and improve performance in memories by splitting the memory array into word line groups (WLGs) which are selectively forward body biased when accessed. We present a derivation of optimal number of WLGs and the forward body bias voltage value, and show that our approach results in a 9:2% access time reduction, and a 53:4% reduction in power during a read operation. Our approach also achieves an 18% reduction in power during a write operation and a 69% leakage power improvement. The area overhead of our scheme is 7:2% compared to a monolithic memory.
Use Search at http://topicideas.net/search.php wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion

Important Note..!

If you are not satisfied with above reply ,..Please


So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page

Quick Reply
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  DESIGN ATM CONTROLLER pdf seminar flower 1 969 22-07-2016, 02:13 PM
Last Post: mkaasees
  detecting power grid synchronization failure jaseelati 2 370 20-05-2016, 12:28 PM
Last Post: Dhanabhagya
  FLEXIBLE POWER ELECTRONIC TRANSFORMER seminar tips 2 1,611 05-07-2015, 09:58 AM
Last Post: tunhtutaye
  MICROCONTROLLER BASED PICK AND PLACE ROBOT projectsofme 10 9,434 21-02-2015, 03:56 AM
Last Post: nalzanbagi
  electronic power generator using transistor jaseelati 0 340 31-01-2015, 01:52 PM
Last Post: jaseelati
  floating power plant ppt jaseelati 0 344 31-01-2015, 12:49 PM
Last Post: jaseelati
  inductive power transfer ppt jaseelati 0 264 23-01-2015, 02:21 PM
Last Post: jaseelati
  high speed electronics devices ppt jaseelati 0 279 23-01-2015, 02:18 PM
Last Post: jaseelati
  power theft detection via plc pdf jaseelati 0 335 22-01-2015, 03:31 PM
Last Post: jaseelati
  distributed power flow controller ppt jaseelati 0 268 21-01-2015, 03:21 PM
Last Post: jaseelati