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Active In SP

Posts: 53
Joined: Nov 2010
16-11-2010, 04:18 PM

Guided By:
Mrs. Sumam M J
Sr. Lecturer
Dept. of ECE
College of engineering, trivandrum
2007-11 batch



Introduction to MMV(Microprocessor Modeling & Validation)
Need for Modeling
Background & Drawbacks of Traditional Validation Environment
Concept of MMV


Validation of Microprocessor
Multiple processing cores
High cost of fixing a bug
Designers model the microprocessor at different levels of abstraction
Single & Multiple Core Processors
Different Levels of Abstraction
Complexity increases as hierarchy goes down
Complexity high at Microarchitecture level due to additional features – out-of-order, superscalar & speculative execution

Need for Modeling
Multiple core processors
Multiple core in single die
Hardware support for applications like virtualization
Multiple cores and the associated communication protocols increase the complexity at the system level abstraction

There is a need for a modeling and validation environment - all levels of abstraction modeled in a uniform manner
The modeling environment should support stepwise manual improvement (e.g., by architects, designers, and validators) and enforce its consistency
Support automatic generation of tools for model analysis
Hence an MMV is proposed
Levels of abstraction analyzed
Develop functional specifications for each level
Goal - microcode, register transfer level (RTL) and the fabricated product in silicon implement the behavior defined in the system, architecture, microcode, and microarchtiecture specifications
Validation Methods
Formal Verification
Specification proven to satisfy a set of properties
Cannot handle large designs due to state space explosion
Simulation Based Validation
Handle large designs
Models of the microprocessor at different levels of abstraction manually derived
RTL/microcode/silicon of the processor is validated

Models and tools are generated from the specification document
Misinterpretation by validators
Rapid changes in the specification during the design and development process
Use of multiple programming languages
Simulators in C/C++
Test generation in ‘Specman e’

MMV – Metamodeling Approach
MMV environment facilitates microprocessor modeling across various abstractions
Uniformly generates code targeted towards various validation platforms
Language-independent modeling syntax and semantics
Uniform way to capture modeling abstractions

express rules that enforce well-defined model construction and consistency
visual editor to facilitate the modeling based on the specified syntax and semantics
capability to plug-in code generators/interpreters to allow for model analysis and translation
Metamodeling is key enabling capability for MMV, provided through GME
The GME is a configurable toolkit that facilitates creation of domain-specific modeling and program synthesis environment

MMV Environment
Metamodeler customizes MMV based on the requirements and creates code generators for different validation
Modeler creates microprocessor models, uses the code generators to generate validation targets.
Modeling modes of MMV
Visually based on microprocessor metamodel (MMM)
Textually based on the microprocessor description language (MDL)
Textual input manages the scalability issue with visual modeling tools
Allows modeler to take advantage of validation tools and checkers
Microprocessor Metamodel (MMM)
The metamodel is built in GME(Generic Modeling Environment) using UML(Unified Modeling Language) constructs and OCL (Object Constraint Language) constraints
Use of UML provides language-independence
Removes modeling restrictions of C/C++ and VHDL/Verilog languages

Abstraction Level Views
MMV’s modeling framework consistently merges the following aspects and provide a multi-abstraction microprocessor model
System-Level View (SV)
Provides protocol-level description of various microprocessor features, considered as a software model
Provides high-level algorithmic specification capability

Entities describing the high-level model need not be refined to the lower abstraction
Entities refined to architectural view, are mapped to one or more sequence of instructions
System-Level View (SV)
Platform acts as a container for the different constituents of a processor
Core, Main_Memory, and entities describe the communication structure
Core is used to describe the CPU of the processor and CoreType attribute is used to inform the framework that an existing core is being modeled

Architecture View (AV)

shows a snapshot of the architectural aspect of the microprocessor metamodel
memory abstraction similar to SV and
does not undergo refinement but uses mem_arch_port to communication with the core
core undergoes a refinement to include register definitions that is described using the RegisterFile entity, used later to map registers to physical addresses

ISA entity provides the language to describe the instruction set
The Instruction entity of the MMM provides the modeler with a language to describe the instruction behavior, which has constructs to write functions, statements and define identifiers

Microarchitecture View (MV)

Core and Main_Memory undergoes a refinement
Virtual memory is made concrete by defining the memory map using the Plocation (provides physical address)

RegisterMap entity maps the defined registers to addresses corresponding to the RegisterFile
The refinements are enforced as constraints to avoid invalid register map functions
Pipeline communicates with the memory to read&write data and address, its functionality can b decscribed using MUX, ALU, Adders etc..
Memport is meant exclusively for system-level communication with the processor core
Main_Memory entity has a new set of ports namely mem_march_ports - renders communication only at MV
Code Generation
In modeling, the metamodel entities are instantiated, characterized, and connected to show the functioning of the microprocessor model
Entity instances and connections are populated into a model database
Translation has two stages:
Extraction process : Model is analyzed in its current abstraction as well as across abstractions and the elements are extracted into homogeneous sets
Target-specific code generation :These sets are interpreted and results in functional simulators, test generator, coverage tools, etc. that allows microprocessor validation.
Metamodeling capability - makes MMV highly customizable and an easily extendible environment
Easily add newer abstractions such as the RTL
Models allows an alternate textual input capability for the tool
Provides a neat and compact way of consistently visualizing model across various abstractions
Allows multi-target code generation
Promotes extendibility by allowing the metamodeler to add newer application-specific targets
D. Moundanos, J. A. Abraham, and Y. V. Hoskote, “Abstraction techniques for validation coverage analysis and test generation,” IEEE Trans. Computers, vol. 47, no. 1, pp. 2–14, Jan. 1998.
A. Adir, E. Almog, L. Fournier, E. Marcus, M. Romon, M. Vinov, and A. Ziv, “Genesys-Pro: Innovations in test program generation for functional processor verification,” in IEEE Design and Test of Computers. Piscataway, NJ: IEEE, 2004.
G. Nordstrom, J. Sztipanovits, G. Karsai, and A. Ledeczi, “Metamodeling – Rapid design and evolution of domain-specific modeling environment,” in Proc. IEEE Conf. Workshop Eng. Comput.-Based Syst.(ECBS) Conf., Apr. 1999, pp. 68–74.
 4. J. Eker, J. W. Janneck, E. A. Lee, J. Liu, X. Liu, J. Ludvig, S. Neuendorffer, S. Sachs, and Y. Xiong, “Taming heterogeneity—the Ptolemy approach,” Proc. IEEE, vol. 91, no. 1, pp. 127–144, Jan. 2003.


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