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computer science crazy
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24-02-2009, 12:13 AM

Nanoelectronics refer to the use of nanotechnology on electronic components, especially transistors. Although the term nanotechnology is generally defined as utilizing technology less than 100nm in size, nanoelectronics often refer to transistor devices that are so small that inter-atomic interactions and quantum mechanical properties need to be studied extensively. As a result, present transistors (such as CMOS90 from TSMC or Pentium 4 Processors from Intel) do not fall under this category, even though these devices are manufactured under 90nm or 65nm technology. Nanoelectronics are sometimes considered as disruptive technology because present candidates are significantly different from traditional transistors. Some of these candidates include: hybrid molecular/semiconductor electronics, one dimensional nanotubes/nanowires, or advanced molecular electronics. The sub-voltage and deep-sub-voltage nanoelectronics are specific and important fields of R&D, and the appearance of new ICs operating near theoretical limit (fundamental, technological, design methodological, architectural, algorithmic) on energy consumption per 1 bit processing is inevitable. The important case of fundamental ultimate limit for logic operation is reversible computing. Although all of these hold immense promises for the future, they are still under development and will most likely not be used for manufacturing any time soon.
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29-06-2010, 07:49 PM

Could u plz snd me the ppt of nanoelectronics plz..
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30-06-2010, 05:31 PM

here is a ppt of nanoelectronics:

.ppt   nanoelectronisc.ppt (Size: 386.5 KB / Downloads: 246)

more ppts are available at the following links:
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09-10-2010, 05:36 PM

.pdf   Adrian_Ionescu.pdf (Size: 1.22 MB / Downloads: 127)

ChallengesAdrian M. IonescuEcolePolytechniqueFédéralede Lausanne, Switzerland


why embracing the ultra-small?
•Research and scientific challenges
•Europe: building on strengths
•Future: investinginnanoelectronicsresearch, infrastructures and education
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14-04-2011, 09:36 AM

.doc   Breif_2.doc (Size: 38 KB / Downloads: 65)
Nanoelectronics the term is the use of nanotechnology on electronic components, mainly transistors. Nanoelectronics often refer to transistor devices that are so small that inter-atomic interactions and quantum mechanical properties need to be studied extensively.
Nanoelectronics plays a major role in making computer processors more powerful than are possible with conventional semiconductor fabrication techniques. A number of approaches are currently being researched, including new forms of nanolithography, as well as the use of nanomaterials such as nanowires or small molecules in place of traditional CMOS components. Field effect transistors have been made using both semiconducting carbon nanotubes and with heterostructured semiconductor nanowires
The characteristics on computer chips are getting small, soon the process used to make them, which has hardly changed in the last 50 years, won’t work anymore. One of the alternatives that academic researchers have been exploring is to create tiny circuits using molecules that automatically arrange themselves into useful patterns.
Nanotechnology, already reached the electronics industry with features in microprocessors now less than 100 nanometres (nm) in size (Intel’s Prescott processor uses 90 nm size features). Smaller sizes allow faster processing times and also more processing power. However, these advances are really only a continuation of existing microelectronics, and will reach their limit sometime around the end of the next decade (2018 or so) when it will be both physically impossible to “write” or “etch” smaller features in silicon, and also because at extremely small sizes (less than 20 nm) silicon becomes electrically “leaky” causing short circuits.
Nanoelectronics on the other hand offer a new approach for the electronics industry in the form of new circuit materials, processors, information storage and even ways of transferring information such as optoelectronics.
MEMS: micro information seekers
Micro-electromechanical system (MEMS) combines computer with tiny mechanical devices such as sensors, valves, gears, and actuators embedded in semiconductor chips. These elements are embedded in the mainframe of the system for carrying out the bigger task. As the elements are capable of carrying out the tasks, they are usually referred to as ‘smart matter’. Minute computers ‘smart dust’ is the brainchild of assistant professor Kris pister. Mr. Pister termed it as ‘motes’. Motes are wireless computers small enough to be integrated into anything to create robust wireless network. Motes act as information seekers and report almost everything on to which they are embedded. Essentially, smart dust is made up of thousands of very minute sensors that can measure ambient light, heat, movement, and sound. These would cost peanuts if mass-produced, could be plastered all over office buildings and homes. Each room in an office building might have a hundred or even thousand light-and temperature-sensing motes, all of which would tie into a central computer that regulates energy usage in the building. This mainly evolved the self assembly chips technology.
The secret of self assembly
Currently, chips are built up, layer by layer, through a process called photolithography. A layer of silicon, metal, or some other material is deposited on a chip and coated with a light-sensitive material, called a photoresist. Light shining through a kind of stencil — a “mask” — project and implimentations a detailed pattern onto the photoresist, which hardens where it’s exposed. The unhardened photoresist is washed away, and chemicals etch away the bare material underneath.
The problem is that chip features are now significantly smaller than the wavelength of the light used to make them. Manufacturers have developed various tricks to get light to produce patterns smaller than its own wavelength, but they won’t work at smaller scales.
The obvious way to continue shrinking chip features would be to use beams of electrons to transfer mask patterns to layers of photoresist. But unlike light, which can shine through a mask and expose an entire chip at once, an electron beam moves back and forth across the surface of a chip in parallel lines, like a harvester working along rows of wheat. The slow, precise scanning of electron-beam lithography makes it significantly more expensive than conventional optical lithography.
Hitching posts
Berggren and Ross’ approach is to use electron-beam lithography, to create patterns of tiny posts on a silicon chip. They then deposit specially designed polymers molecules in which smaller, repeating molecular units are linked into long chains on the chip. The polymers spontaneously hitch up to the posts and arrange themselves into useful patterns.
These days, chips are manufactured with copper wiring surrounded by an insulator, which involves a mask to create circuit patterns by beaming light through the mask and later chemically removing the parts that are not needed. The new technique to make air gaps by self-assembly skips the masking and light-etching process. Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it. This patented process provides the right environment for the compounds to assemble in a directed manner, creating trillions of uniform, nano-scale holes across an entire 300 millimeter wafer. These holes are just 20 nanometers in diameter, up to five times smaller than would be possible using today’s most advanced lithography technique. Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires known as the airgap, allowing the electrical signals to either flow 35 percent faster, or to consume 15 percent less energy.
Research is required, before self-assembling molecules can provide a feasible means for manufacturing individual chips. Berggren and Ross see the technique’s being used to produce stamps that could impart nanoscale magnetic patterns to the surfaces of hard disks, or even to produce the masks used in conventional lithography: the state-of-the art masks for a single chip require electron-beam lithography and can cost millions of dollars. In the meantime, Ross and Berggren are working to find arrangements of their nanoscale posts that will produce functioning circuits in prototype chips, and they’re trying to refine their technique to produce even smaller chip features.
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18-06-2012, 05:59 PM


.ppt   nanoelectronicsfinal-100114091007-phpapp02.ppt (Size: 971.5 KB / Downloads: 43)


According to Moore’s Law, the number of transistors that will fit on a silicon chip doubles every eighteen months.
Presently, microprocessors have more than forty million transistors
By the year 2020, the trend line of Moore’s law states that there should be a one nanometer feature size.


For designing nano FET apart from channel length, other parameters like doping, voltages etc. are to be also scaled.


Technical problem: For channel length<30nm , insulating SiO2 is expected to be less than 2nm thick. This thin layer causes gate dielectric tunneling
Physical problem: For channel length<10nm, direct source-drain tunneling occurs.


RT is observed in hetero-structure semiconductor devices made from pairs of different alloys III-V alloys.
Eg. AlGaAs/GaAs/AlGaAs diodes

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21-08-2012, 09:46 AM

Hey can u plz give me the seminar and presentation report of the nanoelectronics

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