SEQUENTIAL POWER ’ON
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seminar class
Active In SP
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Posts: 5,361
Joined: Feb 2011
#1
24-02-2011, 10:17 AM


PRESENTED BY:
PATEL SNEHAL J.
RATHOD PRADEEP R.
PATEL RAKESH M.
PATEL DIVYESH B.


.pptx   PPT about “SEQUENTIAL POWER ’ON’ ”.pptx (Size: 460.77 KB / Downloads: 105)
SEQUENTIAL POWER ’ON
Introduction

Lot many appliances like air conditioners and refrigerators run in our offices and homes. And almost all of us must have noticed the momentary dimming of the lights when these lights when these loads draw a heavy starting current. The current drawn is so high that other equipment are affected, when all the loads are switched on, very heavy initial current is drawn from the mains.
The sequential power-on circuit presented here switched on the loads one after the other with a regular time delay to avoid the limiting inrush current, especially after mains power resumes. It is designed for switching on 16 appliances with power-‘on’ reset facility.
Project survey & selection
During the survey time for the Project we have selected the followed of topic for our project and implimentation.
• Sequential power ‘ON’
• Security password door locking system
• Transformer protection system
• IR base motor stepper motor controller
• PWM with rpm counter
• High current D.C.motor controller
• Medium power low cost inverter
• Automatic railway gate controller
From above a topic, Sequential Power ‘ON’ was chosen because of following point.
• Easy to operating
• Very useful for over knowledge
• Simple but unique application
• Easy available components
• Useful for low power available place
So we select this topic for our project and implimentation
Circuit Diagram
CIRCUIT DIAGRAM & DESCRIPTION

Fig. shows the circuit of sequential power-on. It comprises optocoupler 4N33, divid-by-12 counter CD-4040, divide-by-16 counter a silicon photo-darlington transistor. AC mains is connected to pin 1 of 4N33 via current-limiting resistor R3. during the positive half cycle, the internal LED of 4N33 is ‘on’ and the phototransistor is driven into saturation and pin 5 goes low. Thus 4N33 provides clock for CD4040 at pin 10.
The CD4040 is a 12-stage ripple-carry binary counter. The counter advances by one cont on the negative transition of each clock pulse. It resets to zero with a logical high at the reset input, independent of the clock. Each counter stage is a static toggle flip-flop. Counter CD4040 further divides the 50hz clock frequency by ‘10’. Output pin 14 provides clock pulse after an interval of 20.48 seconds and also drives 74LS93.
The 74LS93 is a 4-bit binary ripple counter. It consists of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input CP0 and CP1) to initiate state changes of the counter on high to low clock transition. A gated AND asynchronous master reset (pins 2 and 3) is provided, which resets all the flip-flops.
Since the output from the divide-by-two section is not internally connected to the succeeding stages, in a 4-bit ripple counter the Q0 output must be externally connected to CP1 input. The input count pulses are applied to clock input CP0. Simultaneously, frequency divisions of 2, 4, 8 and 16 are performed at Q0,Q1, Q2 and Q3 outputs, respectively. The outputs 74LS93 provide the address inputs to 1-of-16 decoder 74LS154.
The decoder 74LS154 accepts four active-high binary address inputs A0 through A3 and provides 16 mutually exclusive active low outputs O0 through O15. the E0and E1 inputs enable the gate, which can be used either to strobe the decoder for eliminating the normal decoding glitches on the outputs, or for expansion of the decoder. The enable gate has two AND’ed inputs which are made low (by connecting them to ground) to enable the outputs. Outputs O0 through O15 of 74LS154 are connected to the set inputs of flip-flop 74LS74. IC5 through IC12 (each 74LS74) are used as set-reset flip-flops to drive the relays with help of the transistors T1 through T16. the 74LS74 is a dual, positive-edge=triggered, D-type flip-flop featuring individual data, clock, set and reset inputs and also true and complementary outputs. Set input ‘S’ and reset input ‘R’ are asynchronous active-‘low’ inputs that operate independently of the clock inputs. When reset input ‘R’ is high and set input ‘S’ is low, the ‘Q’ outputs goes high to energize the relay.
The ‘Q’ outputs of 74LS74 ICs are connected to the bases of transistors T1 through T16 via resistor R6 through R21, respectively. All the relays (RL1 through RL16) are connected to the collectors of transistors T1 through T16, respectively. Diodes D5 through D20 connected across relays RL1 through RL16, respectively , act as free-wheeling diodes.
B when output pin 5 of flip-flop 74LS74 goes high, transistor T1 is driven into saturation and relay RL1 energizes. Similarly, the high ‘Q’ outputs of other flip-flops drive relays RL2 through RL16.
Flip-flops can energise relays RL1 through RL16 randomly when mains power resumes. To avoid the random energisation of relays, power-‘on’ reset is achieved with NAND gate 74LS00. The NAnd gates are configured as a monostable. Reset pin R of IC2 and IC3 is connected to pin 6 of NAND gate N2. the output of N2 is inverted and connected to reset R input of all the flip-flops. Switch S1 is used for manual reset.
The 230V, 50Hz AC mains is stepped down by transformer X1 to deliver a secondary output of 12V, 500 mA. The transformer output is rectified by a full-wave rectifier comprising diodes D1 through D4, filtered by capacitor C1 and regulated by IC 7805 (IC14), which provides +5V DC output. Capacitor C2 does further filtering. LED1 indicates DC power-‘on’, while resistor R5 acts as a current limiter.
Main components
 4N33optocoupler
 CD4040 divide by 12 counter
 74LS93 binary counter
 74LS154, 1-of-16 decoder
 74LS74, D-type flip-flop
 74LS00 NAND gate
 7805, 5V regulator
 BC337 npn transistor
 Resistor
 1N4007 rectifier diode
 Capacitors
 230V AC primary to 12V,500mA secondary transformer
FEATURES
1. 1-of-16 decorder for signal low to high relay
2. High over loading capacity
3. No use of software program required.
4. Up to 28 I/O points with easy to connect standards headers.
5. Step down transformar
6. Use of CD4040 for counting clock pulse
7. Long life
8. Low maintenance
9. Reset switch
10. Energy saving
11. Cost reduce
Reply
seminar class
Active In SP
**

Posts: 5,361
Joined: Feb 2011
#2
24-02-2011, 10:33 AM

PRESENTED BY:
PATEL SNEHAL J.
RATHOD PRADEEP R.
PATEL RAKESH M.
PATEL DIVYESH B.


.docx   SEQUENTIAL POWER ON .docx (Size: 1.11 MB / Downloads: 92)
1. Introduction:-
Lot many appliances like air conditioners and refrigerators run in our offices and homes. And almost all of us must have noticed the momentary dimming of the lights when these lights when these loads draw a heavy starting current. The current drawn is so high that other equipment are affected, when all the loads are switched on, very heavy initial current is drawn from the mains.
The sequential power-on circuit presented here switcheds on the loads one after the other with a regular time delay to avoid the limiting inrush current, especially after mains power resumes. It is designed for switching on 16 appliances with power-on reset facility.
2. PROJECT SURVEY & SELECTION
During the survey time for the Project we have selected the followed of topic for our project and implimentation.
1. Sequential power ‘ON’
2. Security password door locking system
3. Transformer protection system
4. IR base motor stepper motor controller
5. PWM with rpm counter
6. High current d.c.motor controller
7. Medium power low cost inverter
8. Automatic railway gate controller
From above a topic, Sequential Power ‘ON’ was chosen because of following point.
I. Easy to operating
II. Very useful for over knowledge
III. Simple but unique application
IV. Easy available components
V. Useful for low power available place
So we select this topic for our project and implimentation.
3. CIRCUIT DIAGRAM & DESCRIPTION
Circuit description
Fig. shows the circuit of sequential power-on. It comprises optocoupler 4N33, divid-by-12 counter CD-4040, divide-by-16 counter a silicon photo-darlington transistor. AC mains is connected to pin 1 of 4N33 via current-limiting resistor R3. during the positive half cycle, the internal LED of 4N33 is ‘on’ and the phototransistor is driven into saturation and pin 5 goes low. Thus 4N33 provides clock for CD4040 at pin 10.
The CD4040 is a 12-stage ripple-carry binary counter. The counter advances by one cont on the negative transition of each clock pulse. It resets to zero with a logical high at the reset input, independent of the clock. Each counter stage is a static toggle flip-flop. Counter CD4040 further divides the 50hz clock frequency by ‘10’. Output pin 14 provides clock pulse after an interval of 20.48 seconds and also drives 74LS93.
The 74LS93 is a 4-bit binary ripple counter. It consists of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input CP0 and CP1) to initiate state changes of the counter on high to low clock transition. A gated AND asynchronous master reset (pins 2 and 3) is provided, which resets all the flip-flops.
Since the output from the divide-by-two section is not internally connected to the succeeding stages, in a 4-bit ripple counter the Q0 output must be externally connected to CP1 input. The input count pulses are applied to clock input CP0. Simultaneously, frequency divisions of 2, 4, 8 and 16 are performed at Q0,Q1, Q2 and Q3 outputs, respectively. The outputs 74LS93 provide the address inputs to 1-of-16 decoder 74LS154.
The decoder 74LS154 accepts four active-high binary address inputs A0 through A3 and provides 16 mutually exclusive active low outputs O0 through O15. the E0and E1 inputs enable the gate, which can be used either to strobe the decoder for eliminating the normal decoding glitches on the outputs, or for expansion of the decoder. The enable gate has two AND’ed inputs which are made low (by connecting them to ground) to enable the outputs. Outputs O0 through O15 of 74LS154 are connected to the set inputs of flip-flop 74LS74.
IC5 through IC12 (each 74LS74) are used as set-reset flip-flops to drive the relays with help of the transistors T1 through T16. the 74LS74 is a dual, positive-edge=triggered, D-type flip-flop featuring individual data, clock, set and reset inputs and also true and complementary outputs. Set input ‘S’ and reset input ‘R’ are asynchronous active-‘low’ inputs that operate independently of the clock inputs. When reset input ‘R’ is high and set input ‘S’ is low, the ‘Q’ outputs goes high to energise the relay.
The ‘Q’ outputs of 74LS74 ICs are connected to the bases of transistors T1 through T16 via resistor R6 through R21, respectively. All the relays (RL1 through RL16) are connected to the collectors of transistors T1 through T16, respectively. Diodes D5 through D20 connected across relays RL1 through RL16, respectively , act as free-wheeling diodes.
B when output pin 5 of flip-flop 74LS74 goes high, transistor T1 is driven into saturation and relay RL1 energises. Similarly, the high ‘Q’ outputs of other flip-flops drive relays RL2 through RL16.
Flip-flops can energise relays RL1 through RL16 randomly when mains power resumes. To avoid the random energisation of relays, power-‘on’ reset is achieved with NAND gate 74LS00. The NAnd gates are configured as a monostable. Reset pin R of IC2 and IC3 is connected to pin 6 of NAND gate N2. the output of N2 is inverted and connected to reset R input of all the flip-flops. Switch S1 is used for manual reset.
The 230V, 50Hz AC mains is stepped down by transformer X1 to deliver a secondary output of 12V, 500 mA. The transformer output is rectified by a full-wave rectifier comprising diodes D1 through D4, filtered by capacitor C1 and regulated by IC 7805 (IC14), which provides +5V DC output. Capacitor C2 does further filtering. LED1 indicates DC power-‘on’, while resistor R5 acts as a current limiter.
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