Silicon on insulator technology (SOI)
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21-10-2009, 08:46 PM


Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon dioxide preferred for improved performance and diminished short channel effects in microelectronics devices . The insulating layer and topmost silicon layer also vary widely with application. The first industrial implementation of SOI was announced by IBM
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16-02-2011, 12:53 PM



.ppt   Karthik_soi.ppt (Size: 692.5 KB / Downloads: 239)
Silicon on Insulator
Reasons for SOI

• Replacement for SOS
• Need to extend Moore’s Law
• Commercial Availability of SOI wafers
Advantages of SOI
• Reduced Source and Drain to Substrate Capacitance.
• Absence of Latchup.
• Lower Passive current.
• Denser Layout à Low cost.
SOI Wafer Fabrication
• Bond and Etch Back
• SIMOX (Separation by IMplantation Of oXygen)
• SIMON(Separation by IMplantation Of Nitrogen)
Fully Depleted (FD) SOI
• This is what you expect.
• FDSOI MOSFET
• Depleted channel
Partially Depleted (PD) SOI
• What if active Si layer is thick ?
• Body in channel floating à Floating body effect
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12-04-2011, 02:33 PM

PRESENTED BY:
ARUN KUMAR PANDEY


.docx   Silicon On Insulator.docx (Size: 1.27 MB / Downloads: 76)
INTRODUCTION
SILICON ON INSULATOR (S.O.I.) is a new chip-fabrication technology you might think of as a "chip in a blanket."
Silicon-on-insulator (SOI) chips are made with a layer of silicon dioxide insulation that separates individual transistors from the underlying silicon wafer. In conventional CMOS chips, transistors sit in direct contact with the wafer. SOI's hair-thin blanket of silicon dioxide helps keep electrons flowing efficiently from one transistor gate to another without letting stray electrons leak out into the substrate. The result is a microprocessor in which electrons get to their destinations faster. These chips provide better processing performance; and SOI-based computers use less power because there's no waste due to leaked electrons.
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improve performance. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon dioxide preferred for improved performance and diminished short channel effects in microelectronics devices.
Silicon on Insulator (SOI) substrates are being increasingly used in MEMS applications, with the insulating layers serving as etch stop/sacrificial layers and/or device function layers. Apart from the conventional etching requirements including high etch rate, high selectivity and smooth sidewall, satisfactory etching of SOI wafers requires no notching at the silicon/insulator interface.
WHAT IS SOI ?
Increased demand for High Performance, Low Power and Low Area among microelectronic devices is continuously pushing the fabrication process to go beyond ultra deep sub-micron (UDSM) technologies such as 45nm, 32nm and so on. Currently, chips are being designed in 55nm, 45nm and 32nm process nodes. The performance and power goals for certain applications in these advanced nodes couldn’t be achieved with conventional silicon (bulk CMOS) process leading to an alternative, Silicon On Insulator (SOI) process. Silicon On Insulator fabrication process helps in achieving greater performance and offers less power consumption compared to the Bulk Process.
In a Silicon On Insulator (SOI) Fabrication technology Transistors are built on a silicon layer resting on an Insulating Layer of Silicon dioxide (SiO2). The insulating layer is created by flowing oxygen onto a plain silicon wafer and then heating the wafer to oxidize the silicon, thereby creating a uniform buried layer of silicon dioxide. Transistors are encapsulated in SiO2 on all sides. The below figure shows a typical
NMOS Transistor with Bulk CMOS Process and with SOI Process.
The insulating layer increases device performance by reducing junction capacitance as the junction is isolated from bulk silicon. The decrease in junction capacitance also reduces overall power consumption.
WHY SILICON-ON-INSULATORS ?
 To enhance the performance of Si-devices, SOI is considered, especially when recognizing that only a thin layer from a face of the wafer is used for making the electronic components; the rest essentially serves as a mechanical support.
 The major role of SOI is to electronically insulate a fine layer of the mono-crystalline silicon from the rest of the silicon wafer, beside the ever growing role of W.G.
 Embedded layer of insulation enables the SOI-based chips to function at significantly higher speeds (30 to 40% more) while reducing electrical losses. The result is an increase in performance and a reduction in power consumption by up to up to 50%
 Circuits built in SOI wafers have reduced parasitic capacitance when compared to bulk or epi-wafers.
 Useful for space application as they are immune to radiation-induced single event upset (SEU).
 Free of latch-up.
 Number of masks are reduced by as much as 30%.
FABRICATION OF SOI
Fabrication steps are simpler and less complex :
• Fewer masks and ion implantation steps, made possible by the elimination of well and field isolation implants
• Less complex (costly) lithography and etching required to achieve next-generation performance
Some fabrication process :
- SOS – Silicon-on-Sapphire
- SIMOX – Separation by Implantation of Oxygen
- ZMR – Zone melting and recrystallization
- BESOI – Bond and Etch-back SOI
- Smart-cut SOI Technology
- SIMON (Separation by IMplantation Of Nitrogen)
1. SIMOX - Separation by Implantation of Oxygen
Ion implantation is a materials engineering process by which ions of a material are accelerated in an electrical field and impacted into another solid. This process is used to change the physical, chemical, or electrical properties of the solid. Ion implantation is used in semiconductor device fabrication and in metal finishing, as well as various applications in materials science research. The ions can introduce both a chemical change in the target, in that they can introduce a different element than the target or induce a nuclear transmutation, and a structural change, in that the crystal structure of the target can be damaged or even destroyed by the energetic collision cascades.
One prominent method for preparing silicon on insulator (SOI) substrates from conventional silicon substrates is the SIMOX (Separation by IMplantation of OXygen) process, wherein a buried high dose oxygen implant is converted to silicon oxide by a high temperature annealing process.
Ion implantation equipment typically consists of an ion source, where ions of the desired element are produced, an accelerator, where the ions are electrostatically accelerated to a high energy, and a target chamber, where the ions impinge on a target, which is the material to be implanted. Thus ion implantation is a special case of particle radiation. Each ion is typically a single atom or molecule, and thus the actual amount of material implanted in the target is the integral over time of the ion current. This amount is called the dose. The currents supplied by implanters are typically small (microamperes), and thus the dose which can be implanted in a reasonable amount of time is small. Therefore, ion implantation finds application in cases where the amount of chemical change required is small.
2. Smart-cut SOI Technology
Smart Cut is a technological process that enables the transfer of very fine layers of crystalline material onto a mechanical support. The application of this technological procedure is used mainly in silicon-on-insulator (SOI). The role of SOI is to electronically insulate a fine layer of monocrystalline silicon from the rest of the silicon wafer; an ultra-thin silicon film is transferred to a mechanical support, thereby introducing an intermediate, insulating layer.



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#4
12-04-2011, 04:52 PM

PRESENTED BY:
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PREETAM KUMAR


.pptx   Silicon On Insulator.pptx (Size: 5.58 MB / Downloads: 64)
S.O.I.(SILICON ON INSULATOR)
INTRODUCTION:

 Latest fabrication technology.
 Chip in a Blanket.
 Silicon-on-Silicon.
 Increasing demand for high performance, low power & low area among micro-electronic device led to its invention.
INVENTION:
 SOI (silicon-on-insulator) has been known for ~ 20 years.
 In 1993 Honeywell started product development of SOI to support commercial aircraft electronic engine controls.
 First it was used for military purposes in U.S.A.
What is soi ?
 It is the latest fabrication technique.
 It is easier & cheaper.
 Transistors are build on a silicon layer resting on insulating layer of silicon-di-oxide known as BOX (burried oxide).
 Only a thin layer from a face of the wafer used for making electronic components, the rest essentially serves as mechanical support.
To enhance the performance
 Higher speed.
 Less power consumption.
 Easier fabrication.
 Cheaper etching process.
 More electronic devices can be fabricated on same chip (30% more than bulk).
 It reduces parasitic capacitance when compared to bulk or epi-wafers.
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21-07-2011, 12:25 PM


.pdf   soi.pdf (Size: 394.52 KB / Downloads: 66)
SIMOX
Separation by the IMplantation of OXygen
Silicon bulk wafer
O2 implant
High dose (1018 /cm2), high energy (> 150KeV) implant required
High temperature anneal to react Si and O and remove implant damage
Very low wafer throughput (20 to 40 wafers / day / implanter)
Other SOI specific effects
Fewer processing steps
Better isolation resulting in dense circuits
Lower body effect
Absence of latch-up problem
Better sub-threshold slope
Floating Body Effect – Kink effect, History dependent Vt
Drain current overshoot
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