Stream Processor
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Definition
For many signal processing applications programmability and efficiency is desired. With current technology either programmability or efficiency is achievable, not both. Conventionally ASIC's are being used where highly efficient systems are desired. The problem with ASIC is that once programmed it cannot be enhanced or changed, we have to get a new ASIC for each modification. Other option is microprocessor based or dsp based applications. These can provide either programmability or efficiency. Now with stream processors we can achieve both simultaneously. A comparison of efficiency and programmability of Stream processors and other techniques are done. We will look into how efficiency and programmability is achieved in a stream processor. Also we will examine the challenges faced by stream processor architecture.

The complex modern signal and image processing applications requires hundreds of GOPS (giga, or billions, of operations per second) with a power budget of a few watts, an efficiency of about 100 GOPS/W (GOPS per watt), or 10 pJ/op (Pico Joules per operation). To meet this requirement current media processing applications use ASICs that are tailor made for a particular application. Such processors require significant design efforts and are difficult to change when a new media processing application or algorithm evolve. The other alternative to meet the changing needs is to go for a dsp or microprocessor, which are highly flexible. But these do not provide the high efficiency needed by the application. Stream processors provide a solution to this problem by giving efficiency and programmability simultaneously. They achieve this by expressing the signal processing problems as signal flow graphs with streams flowing between computational kernels. Stream processors have efficiency comparable to ASICs (200 GOPS/W), while being programmable in a high-level language.

Many signal processing applications require both efficiency and programmability. The complexity of modern media processing, including 3D graphics, image compression, and signal processing, requires tens to hundreds of billions of computations per second. To achieve these computation rates, current media processors use special-purpose architectures tailored to one specific application. Such processors require significant design effort and are thus difficult to change as media-processing applications and algorithms evolve. Digital television, surveillance video processing, automated optical inspection, and mobile cameras, camcorders, and 3G cellular handsets have similar needs. The demand for flexibility in media processing motivates the use of programmable processors. However, very large-scale integration constraints limit the performance of traditional programmable architectures. In modern VLSI technology, computation is relatively cheap - thousands of arithmetic logic units that operate at multi gigahertz rates can fit on a modestly sized 1 cm 2 die. The problem is that delivering instructions and data to those ALUs is prohibitively expensive.

For example, only 6.5 percent of the Itanium 2 die is devoted to the 12 integer and two floating-point ALUs and their register files; communication, control, and storage overhead consume the remaining die area. In contrast, the more efficient communication and control structures of a special purpose graphics chip, such as the NVIDIA GeForce4, enable the use of many hundreds of floating-point and integer ALUs to render 3D images. Conventional signal processing solutions can provide high efficiency or programmability, but are unable to provide both at the same time. In applications that demand efficiency, a hardwired application-specific processor-ASIC (application-specific integrated circuit) or ASSP (application-specific standard part)-has an efficiency of 50 to 500 GOPS/W, but offers little if any flexibility.

At the other extreme, microprocessors and DSPs (digital signal processors) are completely programmable but have efficiencies of less than 10 GOPS/W. DSP (digital signal processor) arrays and FPGAs (field-programmable gate arrays) offer higher performance than individual DSPs, but have roughly the same efficiency. Moreover, these solutions are difficult to program-requiring parallelization, partitioning, and, for FPGAs, hardware design. Applications today must choose between efficiency and programmability.
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Stream Processor: Programmability with efficiency




Presented by

VIPIN DAS M.J. Roll no: 659
S7 ECE


Coordinator: Smt. Muneera C.P.

Department of Electronics & Communication Engineering Government Engineering College Thrissur

Abstract




For many signal processing applications programmability and efficiency is desired. With current technology either programmability or efficiency is achievable, not both. Conventionally ASIC's are being used where highly efficient systems are desired. The problem with ASIC is that once programmed it cannot be enhanced or changed, we have to get a new ASIC for each modification. Other option is microprocessor based or dsp based applications. These can provide either programmability or efficiency. Now with stream processors we can achieve both simultaneously. A comparison of efficiency and programmability of Stream processors and other techniques are done. We will look into how efficiency and programmability is achieved in a stream processor. Also we will examine the challenges faced by stream processor architecture.
1. Introduction



The complex modern signal and image processing applications requires hundreds of GOPS (giga, or billions, of operations per second) with a power budget of a few watts, an efficiency of about 100 GOPS/W (GOPS per watt), or 10 pJ/op (Pico Joules per operation). To meet this requirement current media processing applications use ASICs that are tailor made for a particular application. Such processors require significant design efforts and are difficult to change when a new media processing application or algorithm evolve. The other alternative to meet the changing needs is to go for a dsp or microprocessor, which are highly flexible. But these do not provide the high efficiency needed by the application. Stream processors provide a solution to this problem by giving efficiency and programmability simultaneously. They achieve this by expressing the signal processing problems as signal flow graphs with streams flowing between computational kernels. Stream processors have efficiency comparable to ASICs (200 GOPS/W), while being programmable in a high-level language. We will discuss how stream processor is achieves programmability and efficiency at the same time. Also we will look at the tools available for design of stream processing applications and challenges faced in this approach to media processing.
2. Overview


Many signal processing applications require both efficiency and programmability. The complexity of modern media processing, including 3D graphics, image compression, and signal processing, requires tens to hundreds of billions of computations per second. To achieve these computation rates, current media processors use special-purpose architectures tailored to one specific application. Such processors require significant design effort and are thus difficult to change as media-processing applications and algorithms evolve. Digital television, surveillance video processing, automated optical inspection, and mobile cameras, camcorders, and 3G cellular handsets have similar needs. The demand for flexibility in media processing motivates the use of programmable processors. However, very large-scale integration constraints limit the performance of traditional programmable architectures. In modern VLSI technology, computation is relatively cheap - thousands of arithmetic logic units that operate at multi gigahertz rates can fit on a modestly sized 1 cm2 die. The problem is that delivering instructions and data to those ALUs is prohibitively expensive. For example, only 6.5 percent of the Itanium 2 die is devoted to the 12 integer and two floating-point ALUs and their register files; communication, control, and storage overhead consume the remaining die area. In contrast, the more efficient communication and control structures of a special purpose graphics chip, such as the NVIDIA GeForce4, enable the use of many hundreds of floating-point and integer ALUs to render 3D images.


Conventional signal processing solutions can provide high efficiency or programmability, but are unable to provide both at the same time. In applications that demand efficiency, a hardwired application-specific processor”ASIC (application-specific integrated circuit) or ASSP (application-specific standard part)”has an efficiency of 50 to 500 GOPS/W, but offers little if any flexibility. At the other extreme, microprocessors and DSPs (digital signal processors) are completely programmable but have efficiencies ofless than 10 GOPS/W. DSP (digital signal processor) arrays and FPGAs (field-programmable gate arrays) offer higher performance than individual DSPs, but have roughly the same efficiency. Moreover, these solutions are difficult to program”requiring parallelization, partitioning, and, for FPGAs, hardware design.


Applications today must choose between efficiency and programmability. Where power budgets are tight, efficiency is the choice, and the signal processing is implemented with an ASIC or ASSP, giving up programmability. With wireless communications systems, for example, this means that only a

single air interface can be supported or that a separate ASIC is needed for each air interface, with a static partitioning of resources (ASICs) between interfaces.


Stream processors are signal and image processors that offer both efficiency and programmability. Stream processors have efficiency comparable to ASICs (200 GOPS/W), while being programmable in a high-level language.

3. Discussions 3.1 Parallelism and locality

Instruction-Level Parallelism - issuing independent instructions in the same cycle. For example: 6 functional units in an ALU cluster, VLIW - Very Long Instruction Word.
Data-Level Parallelism - performing the same operation on multiple pieces of data. For example: 8 ALU clusters operating on a single stream, Vector computing.
Produce-Consumer Locality-Occurs when one component of a system is producing something that is immediately consumed by another component of the system. The Stream Register File (SRF) and local registers exploit producer-consumer locality.
A stream program (sometimes called a synchronous data-flow program) expresses a computation as a signal flow graph with streams of records (the edges) flowing between computation kernels (the nodes). Most signal-processing applications are naturally expressed in this style. In part, such special-purpose media processors are successful because media applications have abundant parallelism”enabling thousands of computations to occur in parallel”and require minimal global communication and storage”enabling data to pass directly from one ALU to the next. Stream architecture exploits this locality and concurrency by partitioning the communication and storage structures to support many ALUs efficiently:
¢ operands for arithmetic operations reside in local register files (LRFs) near the ALUs, in much the same way that special-purpose architectures store and communicate data locally;
¢ Streams of data capture coarse-grained locality and are stored in a stream register file (SRF), which can efficiently transfer data to and from the LRFs between major computations; and
¢ Global data is stored off-chip only when necessary. These three explicit levels of storage form a data bandwidth
hierarchy with the LRFs providing an order of magnitude more bandwidth than the SRF and the SRF providing an order of magnitude more bandwidth than off-chip storage. This bandwidth hierarchy is well matched to the characteristics of modern VLSI technology, as each level provides successively more storage and less bandwidth. By exploiting the locality inherent in media-processing applications, this hierarchy stores the data at the appropriate level, enabling hundreds of ALUs to operate at close to their peak rate. Moreover, stream architecture can support such a large number of ALUs in an area- and power-efficient manner. Modern high-performance microprocessors and digital signal processors continue to rely on global storage and communication structures to deliver data to the ALUs; these structures use more area and consume more power per ALU than a stream processor.
3.1.1 Streams and kernels


The central idea behind stream processing is to organize an application into streams and kernels to expose the inherent locality and concurrency in media-processing applications. In most cases, not only do streams and kernels expose desirable properties of media applications, but they are also a natural way





yigurt 1 'M$*E(j-2 video encoder {'Example of a stream processing application )
of expressing the application.
This leads to an intuitive programming model that map directly to stream architectures with tens to hundreds of ALUs.
Figure 1 illustrates input and output streams and a kernel taken from an MPEG-2 video encoder. Figure 1 show how a kernel operates on streams graphically. 'Input Image' is a stream that consists of image data from a camera. Elements of 'Input Image' are 16 x 16 pixel regions, or macro blocks, on which the Convert kernel operates. The kernel applies the same computation to the macro blocks in 'Input Image', decomposing each one into six 8 x 8 blocks”four luminance blocks and two 4:1 sub sampled chrominance blocks”and appends them to the Luminance and Chrominance output streams, respectively. 3.1.1(a) Streams
Streams are sets of data elements. All elements are a single data type. Stream elements can be simple, such as a single number, or complex, such as the coordinates of a triangle in 3D space. Streams need not be the same length”for example; the Luminance stream has four times as many elements as the input stream. Further, 'Input Image' could contain all of the macro blocks in an entire video frame, only a row of macro blocks from the frame, or even a subset of a single row.
3.1.1(b) Kernels
Kernels are pieces of code that operate on streams. They take a stream as input and produce a stream as output. Kernels can be chained together. The Convert kernel consists of a loop that processes each element from the input stream. The body of the loop first pops an element from its input stream, performs some computation on that element, and then pushes the results onto the two output streams. Kernels can have one or more input and output streams and performs complex calculations ranging from a few to thousands of operations per input element”one Convert implementation requires 6,464 operations per input macro block to produce the six output blocks. The only external data that a kernel can access are its input and output streams. For example, Convert cannot directly access the data from the video feed; instead, the data must first be organized into a stream.


3.2 Exploiting Parallelism and Locality


As shown in the block diagram of figure 2, a stream processor consists of a scalar processor, a stream memory system, an I/O system, and a stream execution unit, which consists of a micro-

Figure 2: Block Diagram of a Stream Processor
controller and an array of C arithmetic clusters. Each cluster contains a portion of the SRF, a collection of arithmetic units, a set of local register files, and a local switch. A local register file is associated with each arithmetic unit. A global switch allows the clusters to exchange data.
A stream processor executes an instruction set extended with kernel execution and stream load and store instructions. The scalar processor fetches all instructions. It executes scalar instructions itself, dispatches kernel execution instructions to the micro controller and arithmetic clusters, and dispatches stream load and store instructions to the memory or I/O system. For each kernel execution instruction, the micro controller starts execution of a micro program broadcasting VLIW (very-long instruction word) instructions across the clusters until the kernel is completed for all records in the current block.
A large number, CA, of arithmetic units in a stream processor exploit the parallelism of a stream program. A stream processor exploits data parallelism by operating on C stream elements in parallel, one on each cluster, under SIMD (single-instruction, multiple-data) control of the micro controller. The instruction-level parallelism of a kernel is exploited by the multiple arithmetic units in each cluster that are controlled by the VLIW instructions issued by the micro controller. If needed, thread-level parallelism can be exploited by operating multiple stream execution units in parallel. Research has shown that typical stream programs have sufficient data and instruction-level parallelism for media applications to keep more than 1,000 arithmetic units productively employed.2
The exposed register hierarchy of the stream processor exploits the locality of a stream program. Kernel locality is exploited by keeping almost all kernel variables in local register files immediately adjacent to the arithmetic units in which they are to be used. These local register files provide very high bandwidth and very low power for accessing local variables. Producer-consumer locality is exploited via the SRF. A producing kernel, such as the Convert kernel in figure 1, generates a block of an intermediate stream into the SRF, each cluster writing to its local portion of the SRF. A consuming kernel then consumes the block of stream elements directly from the SRF.
While a conventional microprocessor or DSP can benefit from the locality and parallelism exposed by a stream program, it is unable to fully realize the parallelism and locality of streaming. A conventional processor has only a few (typically fewer than four, compared with hundreds for a stream processor) arithmetic units and thus is unable to exploit much of the parallelism exposed by a stream program. A conventional processor is unable to realize much kernel locality because it has too few processor registers (typically fewer than 32, compared with thousands for a stream processor) to capture the working set of a kernel. A processor's cache memory is unable to exploit much of the producer-consumer locality because there is little reuse of consumed data (the data is read once and discarded). Also, a cache is reactive, waiting for the data to be requested before fetching it. In contrast, data is pro actively fetched into an SRF so it is ready when needed. Finally, a cache replaces data without regard to its liveliness (using a least-recently used or random replacement strategy) and often discards data that is still needed. In contrast, an SRF is managed by a compiler in such a manner that only dead data (data that is no longer of interest) is replaced to make room for new data.


3.3 Efficiency


Most of the energy consumed by a modern microprocessor or DSP is consumed by data and instruction movement, not by performing arithmetic. As illustrated in Table 1, for a 0.13um (micrometer) process operating from a 1.2V supply, a simple 32-bit RISC processor consumes 500 pJ to perform an instruction, whereas a single 32-bit arithmetic operation requires only 5 pJ. Only 1 percent of the energy consumed by the instruction is used to perform arithmetic. The remaining 99 percent goes to overhead. This overhead is divided between instruction overhead (reading the instruction from a cache, updating the program counter, instruction decode, transmitting the instruction through a series of pipeline registers, etc.) and data overhead (reading data from a cache, reading and writing a multi port register file, transmitting operands and intermediate results through pipeline registers and bypass multiplexers, etc.).
Table 1 -- Energy per Operation (0.13|um, 1.2 V)
Operation Energy
32-bit arithmetic operation 5 pJ
32-bit re gister read 10 pJ
32-bit 8KB RAM read 50 pJ
32-bit traverse 10mm wire 100 pJ
Execute instruction 500 pJ

A stream processor exploits data and instruction locality to reduce this overhead so that approximately 30 percent of the energy is consumed by arithmetic operations. On the data side, the locality showed in figure 4 keeps most data movements over short wires, consuming little energy. The distributed register organization with a number of small local register files connected by a cluster switch is significantly more efficient than a single global register file.5 Also, the SRF is accessed only once every 20 operations on average, compared with a data cache that is accessed once every three operations on average, greatly reducing memory access energy. On the instruction side, the energy required to read a microinstruction from the microcode memory is amortized across the data parallel clusters of a stream processor. Also, kernel microinstructions are simpler and hence have less control overhead than the RISC instructions executed by the scalar processor.

3.3.1 Time versus space multiplexing


A stream processor time-multiplexes its hardware over the kernels of an application. All of the clusters work together on one kernel”each operating on different data”then they all proceed to the next kernel, and so on. This is shown on the left side of figure 5. In contrast, many tiled architectures (DSP arrays) are space-multiplexed. Each kernel runs continuously on a different tile, processing the data stream in sequence, as shown on the right side of figure 5. The clusters of a stream processor exploit data parallelism, whereas the tiles of a DSP array exploit thread-level parallelism.

Time multiplexing has two significant advantages over space multiplexing: load balance and instruction efficiency. As shown in figure 5, with time multiplexing the load is perfectly balanced across the clusters”all of the clusters are busy all of the time. With space multiplexing, on the other hand, the tiles that perform shorter kernels are idle much of the time as they wait for the tile running the longest kernel to finish. The load is not balanced across the tiles: Tile 0 (the bottleneck tile) is busy all of the time, while the other tiles are idle much of the time. Particularly when kernel execution time is data dependent (as with many compression algorithms), load balancing a space-multiplexed architecture is impossible. A time-multiplexed architecture, on the other hand, is always perfectly balanced. This often results in a 2x to 3x improvement in efficiency.
Exploiting data parallelism rather than thread-level parallelism, a time-multiplexed architecture uses its instruction bandwidth more efficiently. Fetching an instruction is costly in terms of energy. The instruction pointer is incremented, an instruction cache is accessed, and the instruction must be decoded. The energy required to perform these operations often exceeds the energy performed by the arithmetic carried out by the instruction. On a space-multiplexed architecture, each instruction is used exactly once, and thus this instruction cost is added directly to the cost of each instruction. On a time-multiplexed architecture, however, the energy cost of an instruction is amortized across the parallel clusters that all execute the same instruction in parallel. This results in an additional 2x to 3x improvement in efficiency.
3.4 Stream Programming Tools


Mapping an application to a stream processor involves two steps: kernel scheduling, in which the operations of each kernel are scheduled on the arithmetic units of a cluster; and stream scheduling, in which kernel executions and data transfers are scheduled to use the SRF efficiently and to maximize data locality. Researchers of Stanford University have developed a set of programming tools that automate both of these tasks so that a stream processor can be programmed entirely in C without sacrificing efficiency.
Their kernel scheduler takes a kernel described in kernel C and compiles it to a VLIW micro program. This compilation uses communication scheduling to map each operation to a cycle number and arithmetic unit, and simultaneously schedule data movement necessary to provide operands. The compiler software pipelines inner loops, converting data parallelism to instruction-level parallelism where it is required to keep all operation units busy. To handle conditional (if-then-else) structures across the SIMD clusters, the compiler uses predication and conditional streams.
The stream scheduler schedules not only the transfers of blocks of streams between memory, I/O devices, and the SRF, but also the execution of kernels. This task is comparable to scheduling DMA (direct memory access) transfers between off-chip memory and I/O that must be performed manually for most conventional DSPs. The stream scheduler accepts a C++ program and outputs machine code for the scalar processor including stream load and store, I/O, and kernel execution instructions. The stream scheduler optimizes the block size so that the largest possible streams are transferred and operated on at a time, without overflowing the capacity of the SRF. This optimization is similar to the use of cache blocking on conventional processors and to strip mining of loops on vector processors.


3.5 The imagine stream processor


Imagine is a prototype stream processor fabricated in a 0.18um CMOS process. Imagine contains eight arithmetic clusters, each with six 32-bit floating-point arithmetic units: three adders, two multipliers, and one divide-square root (DSQ) unit. With the exception of the DSQ unit, all units are fully pipelined and support 8-, 16-, and 32-bit integer operations, as well as 32-bit floating-point operations. Each input of each arithmetic unit has a separate local register file of sixteen or thirty-two 32-bit words. The SRF has a capacity of 32KB 32-bit words (128KB) and can read 16 words per cycle (two words per cluster). The clusters are controlled by a 576-bit microinstruction. The micro control store holds 2K such instructions. The memory system interfaces to four 32-bit-wide SDRAM banks and reorders memory references to optimize bandwidth. Imagine also includes a network interface and router for connection to I/O devices and to combine multiple Imagines for larger signal-processing tasks.




3.6 Challenges


Stream processors depend on parallelism and locality for their efficiency. For an application to stream well, there must be sufficient parallel work to keep all of the arithmetic units in all of the clusters busy. The parallelism need not be regular, and the work performed on each stream element need not be of the same type or even the same amount. If there is not enough work to go around, however, many of the stream processor's resources will idle and efficiency will suffer. For this reason, stream processors cannot efficiently handle some control-intensive applications that are dominated by a single sequential thread of control with little data parallelism. A streaming application must also have sufficient kernel and producer-consumer locality to keep global bandwidth from becoming a bottleneck. A program that makes random memory references and does little work with each result fetched, for example, would be limited by global bandwidth and not benefit from streaming. Happily, most signal processing applications have adequate data parallelism and locality.
Even for those applications that do stream well, inertia represents a significant barrier to the adoption of stream processors. Though it is easy to program a stream processor in C, learning to use the stream programming tools and writing a complex streaming application still represents a significant effort. For evolutionary applications, it is often easier to reuse the existing code base for a conventional DSP, or the existing net list for an ASIC rather than to develop new streaming code. An application must require both efficiency and flexibility to overcome this inertia.

4. Conclusions


The main competition for stream processors are fixed-function (ASIC or ASSP) processors. Though ASICs have efficiency as good as or better than stream processors, they are costly to design and lack flexibility. It takes about $15 million and 18 months to design a high-performance signal-processing ASIC for each application, and this cost is increasing as semiconductor technology advances. In contrast, a single stream processor can be reused across many applications with no incremental design cost, and software for a typical application can be developed in about six months for about $4 million.10 In addition, this flexibility improves efficiency in applications where multiple modes must be supported. The same resources can be reused across the modes, rather than requiring dedicated resources for each mode that remain idle when the system is operating in a different mode. Also, flexibility permits new algorithms and functions to be easily implemented. Often the performance and efficiency advantage of a new algorithm greatly outweighs the small advantage of an ASIC over a stream processor.
FPGAs are flexible, but lack efficiency and programmability. Because of the overhead of gate-level configurability, processors implemented with FPGAs have an efficiency of 2-10 MOPS per megawatt, comparable to that of conventional processors and DSPs. Newer FPGAs include large function blocks such as

multipliers and microprocessors to partly address this efficiency issue. Also, though FPGAs are flexible, they are not programmable in a high-level language. Manual design to the register-transfer level is required for an FPGA, just as with an ASIC. Advanced compilers may someday ease the programming burden of FPGAs. With competitive energy efficiency, lower recurring costs, and the advantages of flexibility, we expect stream processors to replace ASICs in the most demanding of signal-processing applications.
References


1. William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho
Ahn, and Abhishek Das,( Stanford University ); "Stream
Processors: Programmability with Efficiency", ACM Queue
vol. 2, no. 1 - March 2004
2. Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek
Khailany, Jung Ho, Peter Mattson, John D. Owens;
"Programmable Stream Processors" IEEE Computer, August
2003, pp 54-62.
3. The Imagine - Image and Signal Processor cva.stanford.edu/imagine/
4. OSdata.com: osdatasystem/physical/processor.htm
5. Introduction to DSP - basics borescourses/intro/basics/
6. Ujval Kapasi, William J. Dally, Scott Rixner, John D. Owens, and Brucek Khailany (Stanford University Computer Systems Laboratory); "The Imagine Stream Processor", Proceedings of International Conference on Computer Design, September 16-18, 2002, Freiburg, Germany. cva.stanford.edu/imagine/
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