Tamper-resistance Standardization Research Committee (hereinafter referred to as TSRC
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Tamper-resistance Standardization Research Committee (hereinafter referred to as TSRC)
A three-year-term committee, the Tamper-resistance Standardization Research Committee (hereinafter referred to as TSRC) was established in 2003 within the Information Technology Research and Standardization Center (hereinafter referred to as INSTAC), which is one of the departments of the Japanese Standardization Association (hereinafter referred to as JSA). The purpose of TSRC is to establish the foundations of secure implementation of information technologies (IT) from the viewpoint of standardization by carrying out a study and tackling two research items as follows:
1. Systematic study of various tampering techniques;
2. Development of a method to describe tamper-resistance requirements;
3. Contribution to the international standardization with respect to tamper-resistance.
In 2003 the Security Requirement for Cryptographic Modules became a “New Work Item” for ISO/IEC JTC1 SC27. This was one of the events that triggered the launch of TSRC. On the other hand, there were pressing demand in Japan for secure implementation of cryptographic functions for government and commercial use. This is the context in which TSRC has been focusing on technical study of future items for standardization such as those related to side-channel attacks. Its scope is slightly different from that of the Cryptographic Module Committee of CRYPTREC, another working group in Japan, which aims to create evaluation criteria and test requirements for cryptographic modules to prepare for establishing a CMVP for Japan compliant with the international standard.
Just after its establishment, TSRC decided its direction and started building platforms for experiments. In FY2004, TSRC studied tamper-resistance thoroughly based on theoretical and experimental analysis. TSRC also discussed how to describe requirements for tamper-resistance. In FY2005, TSRC endeavored to contribute to tamper-resistance standardization, including FIPS140 series. More details are described below.
At an early stage of our activities, we recognized the difficulties in handling tamper-resistance issues due to the following points:
(a) Not all attack methods and protection methods can be discussed openly.
(b) A physical target module is required to develop tamper-resistant techniques.
© There is little discussion of evaluation methods for tamper-resistance in the literature.
This situation is quite different from that of cryptographic algorithm research, where open discussion is common, no specific module is required, many criteria for evaluation have been discovered, and a rigorous notion of security has been established. Systematic study of tamper-resistance is intended to overcome these difficulties.
Actions taken by TSRC to solve (a), (b) and © were as follows.
Various invasive or non-invasive attacks have been proposed so far. Some of them are covered by FIPS 140-2. However, we recognize that side-channel attacks are not covered well in the current FIPS in spite of their importance; perhaps because they are relatively new attacks. In addition, there are many descriptions of side-channel attacks in the literature. Therefore, we decided to focus on side-channel attacks. We have surveyed the available literature and categorized those attack methods with respect to the target algorithm. The ultimate goal of this work is to make a comprehensive map or dictionary of side-channel attacks. This is our approach for point