Tri-Gate Transistor
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sravani488
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#1
24-01-2010, 09:03 PM


Please send me some intersting information on this thread not the regular 3Dsize and
heat dissipation
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justlikeheaven
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#2
25-01-2010, 04:46 PM

Tri-gate transistors and methods to fabricate same
This invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication.In a form of the method, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. which is then filled with a semiconductor material. This deposited semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed.

Description
As the scale of integration increases, the present technology of transistor fabrication becomes increasingly obsolete. For example in the present silicon-on-insulator (SOI) transistors are fabricated by coating a substrate with an insulator (e.g., glass or silicon oxide) layer. A second silicon wafer is then bonded to the insulator layer and thinned to a desired thickness . This thinning process is very difficult to control with great accuracy.Here, a portion of the fabrication process for creating a tri-gate SOI transistor is shown. A carrier wafer layer of silicon substrate, has an insulator layer of silicon dioxide deposited on it. a silicon dioxide layer may be grown on a silicon substrate.a transfer wafer is then bonded to the insulator layer to allow for bonding through a heat-induced hydrogen bonding process. The transfer wafer is approximately 600 microns thick.It is is then thinned to a dimension of 50-60 nm through a wet etch and polish process for example. hydrogen implantation method is also used. The bonded pair is then heated to effect a high temperature cleave of the hydrogen-doped interface. Following this, the transfer wafer surface is polished or treated in other ways to planarize the surface or further reduce the thickness. The thickness can be controlled to within a few angstroms(1 angstrom=10^-10 m). the transfer wafer on thinning results in filmlayer. The film layer is then selectively etched using lithography techniques to create silicon bodies for the transistors.
as the gate length, and hence, the desired body height decreases, current fabrication methods exhibit serious disadvantages. The methods of thinning the transfer layer to obtain the film layer are capable of producing a film layer of approximately 20 nm thickness that does not vary by more than approximately 10%. But these methods fail to produce the required uniformity for thinner film layers and hence current methods of fabricating SOI transistors are incapable of yielding transistors with gate lengths smaller than approximately 50 nm. Other than that, the process of bonding the carrier wafer and transfer wafer, and the process of thinning the transfer wafer to the desired thickness are difficult to control and costly.

For full details, follow this link:
patentstorm.us/patents/7268058/fulltext.html


.pdf   Tri-gete transistors and their fabrication.pdf (Size: 183.9 KB / Downloads: 284)
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seminar presentation
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#3
17-05-2010, 10:33 AM

please read topicideashow-to-tri-gate-transistors--4756
topicideashow-to-tri-gate-transistor--6342
topicideashow-to-trigate-transistor for getting more details about trigate transistor informations
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