Understanding Verilog Blocking and Non-blocking Assignments
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13-10-2010, 12:23 PM



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Understanding Verilog Blocking and Non-blocking Assignments

International Cadence
User Group Conference
September 11, 1996
presented by
Stuart Sutherland
Sutherland HDL Consulting

Sutherland HDL Consulting
Verilog Consulting and Training Services
22805 SW 92nd Place
Tualatin, OR 97062 USA

About the Presenter

Stuart Sutherland has over 8 years of experience using Verilog with a variety of software tools. He
holds a BS degree in Computer Science, with an emphasis on Electronic Engineering, and has
worked as a design engineer in the defense industry, and as an Applications Engineer for Gateway
Design Automation (the originator of Verilog) and Cadence Design Systems. Mr. Sutherland has
been providing Verilog HDL consulting services since 1991. As a consultant, he has been actively
involved in using the Verilog langiage with a many different of software tools for the design of
ASICs and systems. He is a member of the IEEE 1364 standards committee and has been involved
in the specification and testing of Verilog simulation products from several EDA vendors, including
the Intergraph-VeriBest VeriBest simulator, the Mentor QuickHDL simulator, and the Frontline
CycleDrive cycle based simulator. In addition to Verilog design consutlting, Mr. Sutherland
provides expert on-site Verilog training on the Verilog HDL language and Programing Language
Interface. Mr. Sutherland is the author and publisher of the popular “Verilog IEEE 1364 Quick
Reference Guide” and the “Verilog IEEE 1364 PLI Quick Reference Guide”.

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