Universal Asynchronous Receiver Transmitter (UART)
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Computer Science Clay
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01-03-2009, 11:00 AM

Universal Asynchronous Receiver Transmitter (UART)

The Universal Asynchronous Receiver Transmitter (UART) is the most widely used serial data communication circuit ever. UARTs allow full duplex communication over serial communication links as RS232. UARTs are available as inexpensive standard products from many semiconductor suppliers, making it unlikely that this specific design is useful by itself.

The basic functions of a UART are a microprocessor interface, double buffering of transmitter data, frame generation, parity generation, parallel to serial conversion, double buffering of receiver data, parity checking, serial to parallel conversion. The data is transmitted asynchronously one bit at a time and there is no clock line.
The frame format of used by UARTs is a low start bit, 5-8 data bits, optional parity bit, and 1 or 2 stop bits. Universal Asynchronous Receive/Transmit consists of baud rate generator, transmitter and receiver. The number of bits transmitted per second is called baud rate and the baud rate generator generates the transmitter and receiver clocks separately. UART synchronizes the incoming bit stream with the local clock.

Transmitter interfaces to the data bus with the transmitter data register empty (TDRE) and write signals. When transmitting, UART takes eight bits of parallel data and converts it into serial bit stream and transmit them serially.
Receiver interfaces to the data bus with the receiver ready and the read signals. When UART detects the start bit, it receives the data serially and converts it into parallel form and when stop bit (logic high) is detected, data is recognized as a valid data.

UART Transmitter

The UART transmitter mainly consists of two eight bit registers the Transmit Data Register (TDR) and Transmit Shift Register (TSR) along with the Transmitter Control. The transmitter control generates the TDRE and TSRE signals which controls the data transmission through the UART transmitter. The write operation into the TDR is based on the signals generated from the microprocessor.
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21-02-2012, 11:57 AM

Universal Asynchronous Receiver Transmitter (UART)

.pdf   CSCE612-Project-2-uart8251-030407.pdf (Size: 646.19 KB / Downloads: 103)

1. UART Functionality
The UART is a universal asynchronous receiver/transmitter, which is modeled on the real-world
Intel® 8251 peripheral interface adapter component. In the model we are considering, the UART
consists of three main blocks.
• a serial transmit block
• a serial receive block and
• a CPU Interface (I/F) block.
The serial transmit block has two buffers (FIFO) into which data is written by the CPU I/F block.
After the data is written into the buffers it is transmitted serially onto TXD. As long as the FIFO
is not full the serial transmit block sets the signal TX_RDY high.
The serial receive block has four buffers (FIFO). The block checks for the parity and the validity
of the data frame on the RXD input and then writes correct data into its buffers. It also sets the
signal RX_RDY low if its FIFO is empty.

2. System partitioning and Component Description
The UART can be divided into several sub-components, according to different functionality.
The description of each of these components is given next section. The block diagram depicting
the more detailed component partitioning is shown in Figures 3 and 4.
The block diagram shows the different components. The D_XS, XCS, DATA, XWR, XRD
inputs are synchronized with the clock by their respective synchronizing blocks each of which
register the signals twice

2.1. The Components

DATASynch: This component registers the DATA signal twice so as to synchronize it with the
system clock CLK16M. The synchronized signal is data_bus1.

DXSSynch: This component registers the D_XS signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is DXS1.

XCSSynch: This component registers the XCS signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is XCS1.

XWRSynch: This component registers the XWR signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is X_WR.

XRDSynch: This component registers the XRD signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is X_RD.

RXDIFF: The RXD input is synchronized with the clock before being read by the receive block.
The synchronized output is r_xd.
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Design Universal Asynchronous Receiver/Transmitter

.docx   Design Universal Asynchronous ReceiverTransmitter.docx (Size: 916.87 KB / Downloads: 35)

This thesis portrays a novel architecture of Universal Asynchronous Receiver Transmitter. UARTs are used for asynchronous serial data communication between remote embedded systems. The UART is for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code.

Synchronous Serial Transmission

Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver.

Receiver Module

The serial receiver section also contains an 8-bit Receiver Buffer Register (RBR) and Receiver Shift Register (RSR). The status of RBR can be provided by either independent pin RxRDYn or the Receiver Data available flag (DR) in LSR.
Since the serial frame is asynchronous to the receiving clock, a high to low transition of SIN pin will be treated as the Start bit of a frame. However, in order to avoid receiving a incorrect data due to SIN signal noise, the False Start Bit Detection feature is implemented in the design which requires the Start bit to be low at least 50% of the receiv- ing baud rate clock cycle. Since the internal clock Clk16X is 16 times the receiving/transmitting baud rate clock fre- quency, the Start bit needs to be low at least 8 Clk16X clocks to be considered as a valid Start bit.

Start Bit Detection

The receiver uses a 16X clock timing. The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (A). The center of the start bit is defined as clock count 7 1/2. If the receiver clock is a symmetrical square wave, the center of the start bit will be located within 1/2 clock cycle, 1/32 bit or 3.125% giving a receiver margin of 46.875%. The receiver begins searching for the next start bit at the center of the first stop bit.

UART Control Register

The UART Control Register (UCR) is a write-only register. Writing a command word to the UCR configures the transmission and reception circuitry. The command word essentially describes the format of characters that are to be transmitted or received. The format of these characters are made up of (1) a specific word length, (2) parity information, and (3) a selected number of stop bits, used to indicate transmission of that character is completed.


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