VHDL (VHSIC Hardware Description Language)
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Computer Science Clay
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01-03-2009, 09:46 AM

VHDL (VHSIC Hardware Description Language)
is a language for describing hardware. Its requirement emerged during the VHSIC development program of the US Department of Defense. The department organized a work shop in 1981 to lay down the specifications of a language which could describe hardware at various levels of abstractions, could generate test signals and record responses, and could act as a medium of information exchange between the chip foundries and the CAD tool operators. However, due to military restrictions, it remained classified till 1985.

1.Building Blocks
To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block.

2.Connecting Blocks
Once we have defined the basic building blocks of our design using entities and their associated architectures, we can combine them together to form other designs. This section describes how to combine these blocks together in a structural description.
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06-04-2012, 04:18 PM


.ppt   VHDL.ppt (Size: 610.5 KB / Downloads: 47)
Resource & references

Fundamentals of digital logic with VHDL design, Brown and Vranesic, Macgraw Hill 2000.
Foundation series software, XILINX student edition (contains a CDROM with design tools for Xilinx), Prentice Hall.

Concept of signals

A signal is used to carry logic information.
In hardware it is a wire.
A signal can be “in” or “out” ..etc.
There are many logic types of signals (wires)
Bit (can only have logic 1 or 0)
Std_logic can be 1, 0 , Z ..etc. ( Z=float.)
Std_logic_vector is a group of wires (called bus).
a, b: in std_logic_vector(3 downto 0); in VHDL
means a(0), a(1), a(2), a(3) are std_logic signals
Same for b.


IN: data flows in, like an input pin
OUT: data flows out, just like an output. The output cannot be read back by the entity
INOUT: bi-directional, used for data lines of a CPU etc.
BUFFER: similar to OUT but it can be read back by the entity. Used for control/address pins of a CPU etc.

Quick revision

You should know
Entity declaration
Use of port()
Modes of IO signals
Structure of a simple Architecture body


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