VHDL (VHSIC Hardware Description Language)
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Computer Science Clay
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30-07-2009, 04:16 PM

VHDL (VHSIC Hardware Description Language) is a language for describing hardware. Its requirement emerged during the VHSIC development program of the US Department of Defense. The department organized a work shop in 1981 to lay down the specifications of a language which could describe hardware at various levels of abstractions, could generate test signals and record responses, and could act as a medium of information exchange between the chip foundries and the CAD tool operators. However, due to military restrictions, it remained classified till 1985.

There was a large participation of the private sector electronics industry in the development of the language. It felt that there was a need to make the language industry standard. In 1985, the DOD granted a permission to hand over the specs to IEEE. Subsequently IEEE released the IEEE 1076/A standard in 1987. It was later revised in 1993. The 1993 revisions are minor and many of the simulation and synthesis tools have not yet adopted them. It is an object-oriented language and therefore people familiar with C++ or PASCAL can grasp it easily. VHDL can wear many hats. It is being used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are the structural, data flow, and behavioral methods of hardware description. Most of the time a mixture of the three methods is employed. The following sections introduce you to the language by examining its use for each of these three methodologies.
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