VITERBI DECODING IN FIELD PROGRAMMABLE GATE ARRAYs (FPGAs) full report
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18-05-2010, 10:16 PM



Presented By:
Syed Shahzad Shah, Faisal Suleman and Saqib Yaqub
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ABSTRACT
Forward Error Correction techniques are utilized for correction of errors at the receiver end. Convolutional encoding is an FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white gaussian noise (AWGN). The Viterbi decoding is one of two types of decoding algorithms used with convolutional encoding-the other type is sequential decoding. Sequential decoding has the advantage that it can perform very well with long-constraint-length convolutional codes, but it has a variable decoding time. In this paper we have implemented Viterbi decoder in a FPGAs. Maximum speed of 68Mbits/second was obtained. The ability to process parallel data paths within the FPGA takes advantage of the parallel structures of the hardware units in Viterbi decoder and therefore, higher speed can be achieved

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aksa-sdspulications/Viterbi_Decoding.pdf
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