VLSI-Very Large Scale Integrated Circuit design report
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09-06-2010, 01:14 PM

.docx   vlsi.docx (Size: 1.47 MB / Downloads: 373)

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Since the invention of the integrated circuit in 19S8,the number of processing steps required to make one has grown from Less than 10 to several hundreds. At the same time-, the silicon wafers on which the VLSI ICs. are produced have gone from being coin sized to being dinner-plate sized. Today one of these 300-mm wafers can yield more than 700 Ics. With such a large number of les coming from a single wafer and with wafers coming off manufacturing lines at rates of tens or thousands a month* companies can quickly find themselves suffering from 1oosses especially in turbulent markets .Batch process which is being followed nowadays by VLSI chip makers is one of the main reasons for these losses. In batch process machines work on a large batch of wafers at the same time and take more than three months to produce VLSI I cs. To avoid the over production of chips ,one method is to go for single wafer process. In single wafer process semiconductor companies will be able to produce chips more quickly when the orders came in in the exact quantities specified by those orders. In this paper the IC- fabrication steps are given in brief. Batch process and the Single wafer process are compared in detai1. In the following years all manufacturers will inevitably adopt single Wafer manufacturing process in order to have fast and cheaper , smaller and good quality chips.

Why Design Integrated Circuits?
Integrated Circuit (IC) technology is the enabling technology for a whole host of innovative devices and systems that have changed the way we live. Integrated circuits are much smaller and consume less power than the discrete components used to build electronic systems before the 1960s. Integration allows us to build systems with many more transistors, allowing much more computing power to be applied to solving a problem. Integrated circuits are also much easier to design and manufacture and are more reliable than discrete systems; that makes it possible to develop special-purpose systems that are more efficient than general “ purpose computers for the task at hand.

Components of Chip:-

An Integrated Circuit (IC) is a combination of interconnected circuit elements inseparably associated on or within a continuous substrate.

The substrate

is the supporting material upon or within which an IC is fabricated or to which an IC is attached.
A monolithic IC is an IC whose elements are formed in place upon or within a semiconductor substrate with at lease one of the elements formed within the substrate.

A hybrid IC consists of a combination of two or more IC types or an IC with some discrete elements.

A wafer (or slice)

is the basic physical unit used in processing. It generally contains a large number of identical ICs, Typically, the wafer is circular; production wafers have a diameter of 4,5 or 6 in. The chip is one of the repeated ICs on a wafer. A typical production wafer may contain as few as 20 or 30 ICs or as many as several hundred or even several thousand, depending upon the complexity and size of the circuit being fabricated. The terms die and bar are used interchangeably for chip in some companies.

A test plug, or process control bar (PCB),

or process control monitor (PCM), is a special chip that is repeated only a few times on each wafer. It is used to monitor the process parameters of the technology. After processing, the validity of the process is verified by measuring, at the wafer probe level, the characteristics of devices and / or circuits on the test plug.
If the measurements of key parameters at the test plug level are not acceptable, the wafer is discarded. Front end construction of components

A test cell, or test lead,

is a special chip repeated only a few times on each wafer. It differs from the test plug in that the circuit designer includes this cell specifically to monitor the performance of elementary sub circuits or subcomponents.

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This article is presented by:
Dr. Stephen Daniels

VLSI Design EE213
Module Aims

Introduction to VLSI Technology
Process Design
Chip Fabrication
Real Circuit Parameters
Circuit Design
Electrical Characteristics
Configuration Building Blocks
Switching Circuitry
Translation onto Silicon
Practical Experience in Layout Design

Learning Outcomes

Understand the principles of the design and implementation of standard MOS integrated circuits and be able to assess their performance taking into account the effects of real circuit parameters


Microwind layout and simulation package
Dedicated to training in sub-micron CMOS VLSI design
Layout editor, electrical circuit extractor and on-line analogue simulator

Attached Files
.ppt   EE213 VLSI Introduction.ppt (Size: 69 KB / Downloads: 186)
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Very-large-scale integration (VLSI)

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complexsemiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into billions of transistors.
The first semiconductor chips held two transistors each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better.
As of early 2008, billion-transistor processors are commercially available. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nmprocesses to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). Another notable example is Nvidia's 280 series GPU. This GPU is unique in the fact that almost all of its 1.4 billion transistors are used for logic, in contrast to the Itanium, whose large transistor count is largely due to its 24 MB L3 cache. Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability).
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.doc   Electronics Seminae (3 D IC TECHNOLOGY).doc (Size: 1.13 MB / Downloads: 87)
There is a saying in real estate, when land get expensive, multi-storied buildings are the alternative solution. We have a similar situation in the chip industry. For the past thirty years, chip designers have considered whether building integrated circuits multiple layers might create cheaper, more powerful chips.
Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnections due to increasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies on one single chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.
The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate interconnection related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC) design. By simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved.
In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that is stacked on top of each other.
The unprecedented growth of the computer and the information technology industry is demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality and performance at minimum cost and power dissipation. Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. A significant fraction of the total power consumption can be due to the wiring network used for clock distribution, which is usually realized using long global wires.
Furthermore, increasing drive for the integration of disparate signals (digital, analog, RF) and technologies (SOI, SiGe, GaAs, and so on) is introducing various SoC design concepts, for which existing planner (2-D) IC design may not be suitable.
In single Si layer (2-D) ICs, chip size is continuously increasing despite reductions in feature size made possible by advances in IC technology such as lithography and etching. This is due to the ever growing demand for functionality and high performance, which causes increased complexity of chip design, requiring more and more transistors to be closely c, has been less positive. Smaller wire cross sections, smaller wire pitch, and longer line to traverse larger chips have increase the resistance and capacitance of these lines, resulting in a significant increase in signal propagation (RC) delay. As interconnect scaling continues, RC delay is increasingly becoming the dominant factor determining the performance of advanced IC’s.
System – on – a –chip (SoC) is a broad concept that refers to the integration of nearly all aspects of a system design on a single chip. These chips are often mixed-signal and/or mixed-technology designs, including such diverse combinations as embedded DRAM, high – performance and low-power logic, analog, RF, programmable platforms (software, FPGAs, Flash, etc.).
SoC designs are often driven by the ever-growing demand for increased system functionality and compactness at minimum cost, power consumption, and time to market. These designs form the basis for numerous novel electronic applications in the near future, in areas such as wired and wireless multimedia communications including high speed internet applications, medical applications including remote surgery, automated drug delivery, and non invasive internal scanning and diagnosis, aircraft/automobile control and safety, fully automated industrial control systems, chemical and biological hazard detection, and home security and entertainment systems, to name a few.
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to get information qabout the topic"VLSI-Very Large Scale Integrated Circuit design report"refer the link bellow

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VLSI-Very Large Scale Integrated Circuit

.doc   report.doc (Size: 665.5 KB / Downloads: 42)

In the modern world people are interested in using compact equipments very large scale integration (VLSI) is the latest technology which steeply reduces the size of equipments.
In this project and implimentation the design of OQPSK using cordic algorithm which produces the very strong versatility and the very good probability frequency and it is applicable for various applications. VLSI chip is designed using VHDL program and implemented using FPGA kit.
Offset quadrature phase-shift keying (OQPSK) is a variant of phase-shift keying modulation using 4 different values of the phase to transmit. It is sometimes called staggered quadrature phase-shift keying (SQPSK).


Daniel M Munoz1, et al (2010) “FPGA based floating-point library for cordic algorithms”.
This paper describes Cordic is particularly well-suited for handheld calculators, an application for which cost (e.g., chip gate count has to be minimized) is much more important than is speed. Also the cordic subroutines for trigonometric and hyperbolic functions can share most of their code.

The main objective of this project and implimentation is to design OQPSK using cordic algorithm which produces the very strong versatility and the very good probability frequency and it is applicable for various applications.


Chapter 1 gives the introduction, objective, literature survey, tools used and organization of the project and implimentation.
Chapter 2 presents a methodology for the design of OQPSK using cordic algorithm which produces the very strong versatility and the very good probability frequency and it is applicable for various applications.

It performs both encryption and decryption with two different cores, Encrypt and Decrypt, respectively. This architecture design is based on RC5 specifications, which define two different schemes: one for encryption and one for decryption.

The primary use of the CORDIC algorithms in a hardware implementation is to avoid time-consuming complex multipliers. The computation of phase for a complex number can be easily implemented in a hardware description language using only adder and shifter circuits bypassing the bulky complex number multipliers

CORDIC is generally faster than other approaches when a hardware multiplier is unavailable (e.g., in a microcontroller based system), or when the number of gates required to implement the functions it supports should be minimized (e.g., in an FPGA).


This paper has done the quite thorough analytical investigation to the OQPSK modulation method with the CORDIC algorithms in a hardware implementation is to avoid time-consuming complex multipliers.


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