Wideband Sigma Delta PLL Modulator full report
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Wide band Sigma-Delta PLL modulator is based on PLL fractional N synthesis techniques along with Sigma-Delta modulation to randomize fractional N spurs. A modified Sigma-Delta function allows for suppression of Sigma-Delta noise at low frequencies & hence allows wider bandwidth. This is achieved using a fractional-N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than the reference frequency. This helps to increase the reference frequency & hence reduces PLLâ„¢s locking time.
One of the major disadvantages of fractional-N PLL is the generation of high tones at multiples of channel spacings. Using digital Sigma-Delta modulation techniques in fractional-N PLL frequency synthesis eliminates this spurs. This is achieved by randomizing the feedback division ratio such that the quantization noise of the fractional-N PLL is transferred to high frequencies. Main advantages of this techniques are small frequency resolution, wide tuning bandwidth &fast switching speed. Low power & low area techniques are used in modified Sigma-Delta modulator. It has a total power consumption of 2mW & 1-GHz operation.
The proliferation of wireless products over past few years has been rapidly increasing. New wireless standards such as GPRS and HSCSD have brought new challenges to wireless transceiver design. One pivotal component of transceiver is frequency synthesizer.
Two major requirements in mobile applications are efficient utilization of frequency spectrum by narrowing the channel spacing and fast switching for high data rates. This can be achieved by using fractional- N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than reference frequency. This will increase the reference frequency and also reduces the PLLâ„¢s lock time.
Fractional N PLL has the disadvantage that it generates high tones at multiple of channel spacing. Using digital sigma delta modulation techniques. we can randomize the frequency division ratio so that quantization noise of the divider can be transferred to high frequencies thereby eliminatory the spurs.
The advantages of this conventional PLL modulator is that they offer small frequency resolution, wider tuning bandwidth and fast switching speed. But they have insufficient bandwidth for current wireless standards such as GSM. so that they cannot be used as a closed loop modulator for digital enhanced codeless (DECT) standard. they efficiently filter out quantization noise and reference feed through for sufficiently small loop bandwidth.
WIDE BAND PLL
For wider loop band width applications bandwidth is increased. but this will results in residual spurs to occur. this due to the fact that the requirement of the quantization noise to be uniformly distributed is violated. since we are using techniques for frequency synthesis the I/P to the modulator is dc I/P which will results in producing tones even when higher order modulators are used. with single bit O/P level of quantization noise is less but with multi bit O/P s quantization noise increases. So the range of stability of modulator is reduced which will results in reduction of tuning range. More over the hardware complexity of the modulator is higher than Mash modulator. In this feed back feed forward modulator the loop band width was limited to nearly three orders of magnitudes less than the reference frequency. So if it is to be used as a closed loop modulator power dissipation will increase.
So in order to widen the loop band width the close-in-phase noise must be kept within tolerable levels and also the rise of the quantization noise must be limited to meet high frequency offset phase noise requirements. At low frequencies or dc the modulator transfer function has a zero which will results in addition of phase noise. For that the zero is moved away from dc to a frequency equal to some multiple of fractional division ratio. This will introduce a notch at that frequency which will reduce the total quantization noise. Now the quantization noise of modified modulator is 1.7 times and 4.25 times smaller than Mash modulator.
At higher frequencies quantization noise cause distortion in the response. This is because the step size of multi bit modulator is same as single bit modulator. So more phase distortion will be occurring in multi bit PLLs. To reduce quantization noise at high frequencies the step size is reduced by producing functional division ratios. This is achieved by using a phase selection divider instead of control logic in conventional modulator. This divider will produce phase shifts of VCO signal and changes the division ratio by selecting different phases from the VCO. This type of divider will produce quarter division ratios.
1. Area of power dissipation was reduced.
2. Quantization noise was reduced.
3. Close-in-phase noise was reduced.
4. Can be used for closed loop applications.
5. Both low frequency and high frequency applications are possible.
6. Fast locking capability of the PLL.
7. High resolution (less than 10 Hz ).
Closed loop parameters.
Bandwidth = 200 KHz
Damping factor = 0.707
Change pump current = 50 micro Amp
VCO gain = 50MHz/V
Comparison with Mash PLL
Parameter proposed PLL Mash PLL
Area 0.71mm2 1mm2
Power 2mw 3mw
Capacitor size 152.56PF 17.58MF
Closed loop BW 200 KHz 30KHz
Close-in-phase noise 1.830 rms 7110 rms
Lock time 15MS 150MS
The modified PLL modulator was implements on a 35mm CMOS technology. The chip includes modulator, frequency driver, phase frequency detector, charge pump and loop filter. An enternal VCO with frequency gain of 50MHz/r was assumed. Control signal for speed up was made enternal. Other pins include and bit frequency control hord and enable signal. Separate supply voltages were used for driver, charge pump and digital circuitry is mainly nominated by modulator and control interface.
In order to reduce power consumption supply voltage was reduced to 1.5 pipelining was used to compensate for loss in performance due to low supply voltage. So the power consumption was about 4.5 times reduced. The figure shows the power consumed by various components. The minimum lock time required for 100th resolution is less than 15MS. Less stand by power can be achieved since the time that the receiver must remain on channel scanning is reduced. The figure shows the locking characteristics of the PLL.
FREQUENCY SPECTRUM OF PLL:
The frequency spectrum of PLL is given below.
The notch frequency is of 200KHz. The quantization noise is very much suppressed at 200KHz. Also notice that the phase noise at 3MHz is â€œ64dBc for a frequency resolution of 10KHz or â€œ144dBc/Hz, which meets the GSM specification. Notch frequencies at 400,600 &800KHz were also simulated. These simulations revealed no significant advantage over the notch filter with 200KHz. This is due to the fact that the further away the notch frequency is located, the more close-in-phase noise is allowed to accumulate over the close -loop bandwidth.
Sigma-Delta PLL modulator is implemented as an error feedback configuration. For a 3-bit modulator four notch frequencies are available. A data path width of 21-bit is used while the reference frequency is taken as 13 MHz. A high level diagram of the modulator is shown below.
The multipliers that contribute negligibly to the O/P are avoided. Also third order notch filtering reduces a dot product operation to a simple negation. Number of parallel adders is reduced by merging all addition operation to a 20 I/P adder. Circuit To reduce the complexity of the hardware (divider) several optimizations were involved. First, the partial products of complexity is further reduced by truncating sufficient bits without altering the transfer function.
This is the largest block in the modified Sigma-Delta modulator. Optimizing this will reduce the area & power consumption. Implementation involves using a carry save tree (CST). But this cannot handle negative numbers. So addition of multi-input operands without sign extension can be possible. In the proposed algorithm the MSB is given a negative weight. So twoâ„¢s complement addition of two operands is possible. Four possible combination of addition are
( C, S ) =X+Y+Z
( C,- S ) = -X+Y+Z
(-C ,S ) = -X-Y+Z
( -C,-S ) = -X-Y-Z
Using this method chip area &power is very much reduced. Modified diagram of PLL modulator is given below.
FINAL STAGE FULL ADDER
CST reduces 20 operands to two operands. Then a ripple adder with at most one I/P may be negatively is used. So the O/P of each full adder cell may have either positive or negative terms. Since either of the I/P is negative the sum may be negative. To avoid this carry-in & carry-out signals can take values [-1,0,1]. So the B I/P is also ranging from [-1,0,1].
BINARY REPRESENTATION OF CARRY SIG
C OUT C OUT P C OUT N
-1 0 1
0 0 0
1 1 0
Dither generator is used in this is based on linear feedback shift register (LFSR). It is used as a pseudo random number generator. The period of the generator depends on the number of bits of LFSR.
Usually multi modulus divider with asynchronous divider structure is used in the modified Sigma-Delta modulator. The first section is a high speed multiplexing circuit which is used to implement a divide-by-1/1.25/1.5/1.75 cells. The phase selection divider operates at the VCO frequency. So we need a high logic to implement this stage. So multiplexer stage is operating at VCO frequency. For that we are using current mode logic (CML). CML is capable of operating at VCO frequency. One major advantage of CML is that several logic functions can be cascaded into one gate. The rest of the divider consists of cascade of divide-by-2/3 cells. The total division of this structure is 64 to 127.75 in quarter steps. Gated logic was used to implement the divide-by-2/3 cells to avoid the large control logic needed for phase selection. The diagram of phase selection divider is given below.
The use of gated logic for divide-by-2/3 cells greatly simplifies the gated logic. A proposed method of avoiding the linear growth of control logic with increase in divider size is given below.
CHARGE PUMP CIRCUIT:
The design of charge pump is critical in eliminating dead zone as well as in reducing the close-in-phase noise of PLL modulator. This in turn aids the performance of the PLL modulator. The switching time of the charge pump is also critical. For fast switching, a current steering type charge pump is used. This avoids turning charge pump current sources ON&OFF, which helps to reduce the time it takes for the current switches to settle.
COMPARISON WITH MASH SIGMA-DELTA MODULATOR
Parameter Proposed Sigma-Delta modulator Mash Sigma-Delta modulator
Dominant loop filter capacitor size
15 micro sec
150 micro sec
A wide band PLL modulator for wireless applications is reported. This modulator is based on PLL fractional â€œN frequency synthesis techniques along with modulation to randomize fractional-N spurs. The modified function allows for suppression of noise at low frequencies and hence allows wider loop band width. Also quantization noise is reduced by using a truly differential logic implementation of fractional phase selection divide. The wide band width of 200KHz makes the proposed PLL suitable closed loop modulation.
1. IEEE TRANSACTIONS ON CIRCUITS&SYSTEMS
2. IEEE J. SOLID STATE CIRCUITS DECâ„¢ 97
3. IEEE J. SOLID STATE CIRCUITS MAYâ„¢ 93
FREQUENCY SPECTRUM OF PLL:
COMPARISON WITH MASH SIGMA-DELTA MODULATOR
I extend my sincere thanks to Prof. P.V.Abdul Hameed, Head of the Department for providing me with the guidance and facilities for the Seminar.
I express my sincere gratitude to Seminar coordinator
Mr. Berly C.J, Staff in charge, for their cooperation and guidance for preparing and presenting this seminar and presentation.
I also extend my sincere thanks to all other faculty members of Electronics and Communication Department and my friends for their support and encouragement.
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25-03-2011, 10:15 AM
Wide and sigma DELTA PLL MODULATOR
Wide band Sigma-Delta PLL modulator is based on PLL fractional N synthesis techniques along with Sigma-Delta modulation to randomize fractional N spurs. A modified Sigma-Delta function allows for suppression of Sigma-Delta noise at low frequencies & hence allows wider bandwidth. This is achieved using a fractional-N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than the reference frequency. This helps to increase the reference frequency & hence reduces PLL’s locking time.
One of the major disadvantages of fractional-N PLL is the generation of high tones at multiples of channel spacings. Using digital Sigma-Delta modulation techniques in fractional-N PLL frequency synthesis eliminates this spurs. This is achieved by randomizing the feedback division ratio such that the quantization noise of the fractional-N PLL is transferred to high frequencies. Main advantages of this techniques are small frequency resolution, wide tuning bandwidth &fast switching speed. Low power & low area techniques are used in modified Sigma-Delta modulator. It has a total power consumption of 2mW & 1-GHz