cellular neural networks
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28122009, 04:37 PM
CELLULAR NEURAL NETWORKS.zip (Size: 1.13 MB / Downloads: 248) CELLULAR NEURAL NETWORKS Abstract.doc (Size: 125 KB / Downloads: 171) CELLULAR NEURAL NETWORKS images.zip (Size: 193.66 KB / Downloads: 134) CELLULAR NEURAL NETWORKS SLIDE.doc (Size: 235 KB / Downloads: 184) ABSTRACT Is a revolutionary concept and an experimentally proven computing paradigm for analog computers. A standard CNN architecture consists of an m*n rectangular array of cells c(i,j) with Cartesian coordinates. Considering inputs and outputs of a cell as binary arguments. It can realize Boolean functions. using this technology, analog computers mimic anatomy & physiology of many sensory& processing organs with stored programmability. this has been called sensor revolution with cheap sensors &mems arrays in desired forms of artificial eyes, ears, nose etc. Such a computer is capable of computing 3 trillion equivalent digital operations/sec, a performance that can be only matched by super computers. CNN chips are mainly used in processing brainlike tasks due to its unique architecture which are nonnumeric &spatio temporal in nature and will require no more than accuracy of common neurons. INTRODUCTION Cellular Neural Network is a revolutionary concept and an experimentally proven new computing paradigm for analog computers. Looking at the technological advancement in the last 50 years ; we see the first revolution which led to pc industry in 1980â„¢s, second revolution led to internet industry in 1990â„¢s cheap sensors & mems arrays in desired forms of artificial eyes, nose, ears etc. this third revolution owes due to C.N.N.This technology is implemented using CNNUM and is also used in imageprocessing.It can also implement any Boolean functions. ARCHITECTURE OF CNN A standard CNN architecture consists of an m*n rectangular array of cells c(i,j) with Cartesian coordinates (i,j) i=1,2Â¦..M, j=12Â¦...N. A class 1 m*n standard CNN is defined by a m*n rectangular array of cells cij located at site (i,j) i= 1,2 Â¦Â¦.m ,j=1,2,Â¦.n is defined mathematically by (dXij/dt )= Xij + ? A(I,j,k,l) Ykl + ?B(i,j,k,l) + Zij ELECTRONIC CIRCUIT MODEL OF CNN Voltage controlled current sources impliment various coupling terms. These transconductances can be easily constructed on CMOS integrated circuits CNN TEMPLATES EDGE DETECTION TEMPLATE Local rules 1. White pixel white, independent of neighbours 2. Black pixel white , if all nearest neighbours are black 3. Black pixel black , if at least one nearest neighbour is white 4. Black, gray or white pixelgray if nearest neighbours are gray DIGITAL HARDWARE ACCELERATORS We can emulate analog dynamics by digital hardware accelerators. Emulating large CNN arrays need more computing power. A special hardware accelerator board (HAB) was developed for simulating up to one million pixel arrays with on board memory, with 4 DSP chips. Using habâ„¢s large arrays can be simulated with cheap pc. Actually the DSP is a reduced instruction set (RISC). Processor used for calculating CNN dynamics New dsp packages host 48 dsp processors in a chip .hence the process numbers are 48 times higher .since for the calculation of CNN dynamics ,a major part of dsp is not used , a special purpose chip (castle) have been developed SIMPLICAL CNN Recently a novel structure has been introduced to implement any Boolean / gray level function of any number of variables .The output is no longer restricted to be binary so that CNNs with gray scale outputs are obtained. Simplical CNNs are implemented using RTDs (resonant tunneling diodes) RTDs are nano electric quantum device is featuring high speed regims and small integration sizes and they can be designed to operate in nano /femto sizes leading to extreme low power designs. In addition they exhibit an intrinsic non linear behaviour which can be exploited in many diverse applications, for instance in frequency multiplier and parity generators the threshold logic gates multi gigahertz ad converters, and multivalued logic applications including multivalued memory design among others. A simplical partition is used to subdivide the domain in to convex regions called simplices which are the natural extension 2d triangle into an nd space the corners of these simplices are called vertices & for the particular chosen domain are the points of the form ( +1,1,+1,1) it was proven that the set of all PWL function f is a linear vector space. Every PWL function can be expressed as a linear combination F= â€šÂ¬ CiAi (u) Ai(vj)=1, if i=j VERTEX  CODE GENERATION The first step is to identify the simplex that contains the given input vector u.Notice here that there are n! different simplices in (3), and every simplex is identified by the coordinates of its n+ 1 vertex. This mechanism is based on the result, U= ? B Vij This mechanism can be realized using a mixed signal circuit architecture illustrated where an array of comparators compare components input to ramp signal. In this scheme vertex codes can be read at the outputs of comparators. PARAMETER RETRIEVAL Once a vertex vi has been identified the second step is obtained ci= f(vi) .in the circuit scheme this is accomplished by memory block. INTER POLATION Once all the vertices &their corresponding values have been obtained the final value f(u) is obtained by interpolation at the vertices . Then, F = ? Ci*Bi In the circuit this operations is executed by the output capacitor, due to the fact that the fraction of time every function value ci=f(vi) is present at the output of the memory block is proportional to bi .Finally note that in general r<=n+1 is much smaller than q.In fact if n=9 r<=n+1=10 and q=29=512.From the point of view of a 3*3 sphere of influence C.N.N cell , this implies that even though the function has 29 parameters, its evaluation requires at most the implementation of linear combination of 10 terms . IMPLEMENTATION OF SIMPLICAL R.T.D. C.N.N. The first block is responsible for vertex code generation, whereas the second block is responsible for producing the values of function at the vertices . Finally there is the interpolation state , which is the charge of producing the result VERTEX CODE GENERATOR The vertex code generator is the part of the circuit that receives as input the nine values {u1, u2, Â¦u9}. Corresponding to the inputs associated with central pixel and its 8 neighbours & generate s a code. This code is used to retrieve the value of associated parameter . The key component of vertex code generator is a comparator . One way to implement this is using a single r.t.d in current mode configuration as in the circuit illustrated below. In this circuit the inputs ui & uramp are current signals which are subtracted & then fed into r.t.d. using conventional mirrors. The qualitative temporal response of the cell to an arbitrary pair of input signals is illustrated in figure. at the beginning of the cycle the signal vreset goes high & ensures that the initial condition of the r.t.d. corresponds to a voltage greater than vh in order to assure the switching when the current crosses zero this is necessary to subtract from r.t.d. characteristics the constant value of valley current Iv PARAMETER GENERATOR In general r <= n+1 is much smaller than q if n= 9,r<= n+1 =10 & q=pow(2,9) .from the point of view of a 3*3 sphere of influence C.N.N cell , this implies that even though the function has pow(2,9) parameters ,its evaluation requires at most the implementation of a linear combination of 10 terms . The analogue value belongs to interval (0,1). the function of second block is to produce the correct value ci whenever its code is present the output of the vertex code generator we use a standard 512 bits sram in which the parameters are quantized using 2 levels . SRAM APPROACH In this case every parameter of the simplical p.w.l. function is represented with just 2 states. This allows an extremely versatile implementation due to the fact that the parameters can be stored in a digital sram indeed this block can be integrated using r.t.d. devices. Actually an r.t.d. hetero structure FET, SRAM, gaincell in an INP based martial system has been reported & based on na.r.t.d. this cell utilizes a pair of series connected r.t.d's & one transistor to store one bit by exploiting the two stable equilibrium states of r.t.d. the one t sram cell exhibits excellent high frequency characteristics with cutoff frequency and maximum frequency of oscillation over 100 GHz . recently another approach based on a slew rate based accessing method has been reported which allows to store and access n bits in a series connection of n vertically integrated r.t.ds. The q writes FET works as a variable resistor whose value is set by the voltage in the word line. The bit line is activated with a step and the RC combination determines the slew rate that activates the corresponding r.t.d. C.N.N. UNIVERSAL MACHINE The first spatio temporalanalogic array computer is CNN universal machine. The two different operations are continoustime, continues valued spatiotemporal nonlinear array dynamics (2d$3darrays) local & global logic hence analog &logic operations are mixed and embedded in array computer. Therefore we call this type of computing: analogic. The CNNUM architecture (1) It has a minimum number of component types (2) Provides stored programmability spatio temporal array computing (3) Is universal in two sense: As spatial logic, it is equivalent to a Turing machine and as a local logic it may compute any Boolean function. As a nonlinear dynamic operator, it can realize any local operator of fading memory. the CNN UM is a common computational paradigm for as diverse fields of spatiotemporal computing as for example, retinal model, reaction diffusion equations, mathematical morphology, etc. The stored program ,as a sequence of templates is considered as a genetic code of CNN UM. The elementary genes are the templates. THE ARCHITECTURE The local analogic output unit is a multiple inputsingleoutput analog device. Which combines: (i) Local analog values into a single output. The local communication & control unit (i) receives the programming instructions, in each cell from the Global Analogic Programming Unit(GAPU) , namely 1. The analog values(A,B&z) 2. The logic local unit, and 3. The switch configuration of the cell specifying the signal paths &some settings in the functional units. We need an analog program register(APR)logic program register for the CNN templates, a Logic Program Register for LLU functions & a switch configuration register(SCR) in the figure given analog part of the schematic of the cell is shown. we assign a separate local analog memory place for the input(u), initial state(x(0)), threshold(z), a sequence of outputs(yn), for all these signals &data. GAPU(GLOBAL ANALOGIC PROGRAMMING UNIT) This unit is the "conductor of the whole analogic CNN universal machine it directs all the extended standard CNN universal cells. GAPU is the machine code of the sequence of instructions of the given analogic c.n.n program. WHY STORED PROGRAMMIBILITY IS POSSIBLE? In computers, we tacitly assume and take for ranted that, for any sequence of instructions: (a) All the transients decay with in a specified clock cycle,& (b) All the signals remain with in a prescribed range of dynamics (including dissipation, slope, etc.). A unique feature of the CNN dynamics & the CNNUM architecture is that we can assure conditions (a) & (b) as well. It is much less trivial here than in the digital case .Our main elementary instructions are the CNN templates & the local logic operations. But the CNN templates may induce the most exotic dynamics . the global clock( GCL) has a faster clock cycle for the logic part than for the analog part. The global analogic control unit stores, in digital form, the sequence of instructions. each instruction contains the operation code(template or logic),the selection code for the parameters of the operations(the code for the 19 values: a, b & z ; or the code of the local logic function),&the switch configuration. The parameters are stored in the registers (APR, LPR, SCR). VISUAL MICROPROCESSORS ANALOGUE & DIGITAL VLSI IMPLEMENTATION OF C.N.N U.M. The peculiarity of stored programmability makes it possible to fabricate visual microprocessors. THE ANALOGUE CNN CORE There are only three building blocks in the core cell: a capacitor, a VCCS & a resistor the CMOS the implementation of a capacitor is straight forward, the transistor by a resistor & the VCCS by operational trans conductance amplifiers called synapse circuits. This cell model is called chuayang model APPLICATIONS 1) cheap sensors and mems arrays are in the desired forms of artificial eyes, nose, ears, taste & realization of telepathy 2) high speed target recognition, tracking 3) real time visual inspection of manufacturing processes 4) in terms of speed, power, area this chip is far superior to any equivalent dsp implementation at least three orders of magnitude in either s ,p or a 5) intelligent vision capable of recognition of contextsensitive & moving scenes as well as applications requiring real time fusing of multiple modalities such as multi spectral images involving infrared, long waveinfrared and polarized lights. CONCLUSION Optical implementation is already emerging using molecular level optical memory & atomic & molecular level implementation of c.n.n. array as well as CNNUM may become feasible. PDE based in modern image processing techniques are becoming most challenging & important for analogic c.n.n. computers. A major challenge yet not solved by any existing technology is to build analogic adaptive sensor computer where sensing & computing understanding are fully integrated on a chip. REFERENCES 1) IEEE transactions on circuits & systems, April 2003. 2) pedrojulian.com. CONTENTS ? INTRODUCTION ? ELECTRONIC CIRCUIT MODEL OF C.N.N. ? C.N.N. TEMPLATES ? DIGITAL HARDWARE ACCELERATORS ? SIMPLICAL C.N.N. ? VERTEX CODE GENERATION ? PARAMETER RETRIEVAL ? INTER POLATION ? IMPLEMENTATION OF SIMPLICAL C.N.N. ? C.N.N. UNIVERSAL MACHINE ? VISUAL MICROPROCESSORS ANALOGUE & DIGITAL VLSI IMPLEMENTATION OF C.N.N U.M. ? APPLICATIONS ? CONCLUSION ? REFERENCES ACKNOWLEDGEMENT I extend my sincere thanks to Prof. P.V.Abdul Hameed, head of the department for providing me with the guidance and facilities for the seminar and presentation. I express my sincere gratitude to seminar and presentation coordinator Mr. Berly C.J, staff in charge, for their cooperation and guidance for preparing and presenting this seminar and presentation. I also extend my sincere thanks to all other faculty members of electronics and communication department and my friends for their support and encouragement. PRASOON. P Use Search at http://topicideas.net/search.php wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion



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23042011, 04:40 PM
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DEEPA RANI PATRO techsem_ppt_191.ppt (Size: 464.5 KB / Downloads: 48) CELLULAR NEURAL NETWORK INTRODUCTION Cellular Neural Networks (CNNs) is a paradigm of mostly locally connected networks of simple nonlinear processors in discrete Ndimensional spaces. Cells are multiple inputsingle output processors, all described by one or just some few parametric functionals which control the cell interconnection strength. Cell interconnect is local, meaning that all connections between cells are within a specified radius, where distance is measured topologically which allows also to obtain global processing. Connections can also be timedelayed to allow for processing in the temporal domain. This exhibits spaceinvariance property. Dynamics are usually • ContinuousTime CNN (CTCNN) processors DiscreteTime CNN (DTCNN) processors FEATURES OF CNN The CNN can be defined as an M x N type array of identical cell arranged in a rectangular grid.Each cell is locally connected to its 8 nearest surrounding neighbors. Each cell is characterised by uij, vij and xij being the input, The output and the state variable of the cell respectively. The output is related to the state by the nonlinear equation: vij = f(xij) =o.5( xij + 1   xij  1) The state transition of the cell C(i,j) is governed by the following differential equation: The coefficients are known as cloning templates which are generally nonlinear and time and space variant operators. Structure of single CNN cell The node voltage Vxij is called the state of the cell . The node voltage Vuij is called the input of c(i,j) . The node voltage Vyij is called the output. DISCRETE TIMECNN A DTCNN poses a regular grid of locally connected cells. The DTCNN is a clocked system; whose dynamics are described by a set of discrete equations. A cell ‘C’ is identified by the coordinate of its position in the grid, i.e. row Ci and column Cj and communicates directly with all the neighbor cells belonging to the rneighborhood. The character d represents any cell belonging to the neighborhood of cell C, including C itself. Equation below depicts the dependencies of state of a cell C, denoted xc on input ud and the timevariant output yd at a discrete time k. The functionality of DTCNN cell is depicted by CNNUNIVERSAL MACHINE It is the first spatiotemporal analogic array computer. The two different operations are • continuoustime, continuous valued spatiotemporal nonlinear array dynamics (2d$3darrays) local & • global logic • As both analog & logic operations are mixed and embedded in array computer, this type of computing is called analogic. 


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02052011, 01:37 PM
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