password-authenticated key agreement using smart cards for campus management
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24-06-2010, 11:29 AM

.doc   robust and efficient password-authenticated key agreement using smart cards for campus management.doc (Size: 920.5 KB / Downloads: 166)



The main objective of this project and implimentation is to develop an embedded system, which is used for security for the campus management. In this security system the specific persons can only enter into the campus; by using this embedded system we can give access to the authorized people through the RFID tags and keypads.
The embedded system is going to be developed based on microcontroller; when ever the student puts the RFID card on the reader the reader will send the student information to the embedded system then it asks for pin. RFID card reader module will be interfaced to the microcontroller and the pin is entered through the keypad. If the entered password is correct, then only the students will have the authentication to enter into the campus.
The system is programmable we can change the data of the authorized people in the data base of the embedded system; we can access the data on the embedded system on to computer. The complete code for the embedded system is going to be developed using C-Language.

The system uses a compact circuitry built around ARM microcontroller Programs are developed in Embedded C. Flash magic is used for loading programs into Microcontroller.
SOFTWARE: Embedded ËœCâ„¢
TOOLS: Keil, Flashmagic.
TARGET DEVICE: LPC 2148(ARM7) microcontroller.
APPLICATIONS: Home and office appliances.
ADVANTAGES: Low cost, automated operation, Low Power consumption.


1. Introduction to Embedded Systems
2. ARM and Its Architecture
3. LPC2148 Microcontrollers
4. RFID Modules, Relay, LCD
5. Working flow of the project and implimentation Block diagram and Schematic diagram
6. Source code
7. Keil software
8. Conclusion
9. Bibiliography




An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, sometimes with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Embedded systems have become very important today as they control many of the common devices we use.
Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale.

Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure.

In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, Handheld computers share some elements with embedded systems ” such as the operating systems and microprocessors which power them ” but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected.

An embedded system is some combination of computer hardware and software, either fixed in capability or programmable, that is specifically designed for a particular kind of application device. Industrial machines, automobiles, medical equipment, cameras, household appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone and PDA) are among the myriad possible hosts of an embedded system. Embedded systems that are programmable are provided with a programming interface, and embedded systems programming is a specialized occupation.

Certain operating systems or language platforms are tailored for the embedded market, such as Embedded Java and Windows XP Embedded. However, some low-end consumer products use very inexpensive microprocessors and limited storage, with the application and operating system both part of a single program. The program is written permanently into the system's memory in this case, rather than being loaded into RAM (random access memory), as programs on a personal computer are.


We are living in the Embedded World. You are surrounded with many embedded products and your daily life largely depends on the proper functioning of these gadgets. Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in your kitchen, Card readers, Access Controllers, Palm devices of your work space enable you to do many of your tasks very effectively. Apart from all these, many controllers embedded in your car take care of car operations between the bumpers and most of the times you tend to ignore all these controllers.

In recent days, you are showered with variety of information about these embedded controllers in many places. All kinds of magazines and journals regularly dish out details about latest technologies, new devices; fast applications which make you believe that your basic survival is controlled by these embedded products. Now you can agree to the fact that these embedded products have successfully invaded into our world. You must be wondering about these embedded controllers or systems. What is this Embedded System

The computer you use to compose your mails, or create a document or analyze the database is known as the standard desktop computer. These desktop computers are manufactured to serve many purposes and applications.
You need to install the relevant software to get the required processing facility. So, these desktop computers can do many things. In contrast, embedded controllers carryout a specific work for which they are designed. Most of the time, engineers design these embedded controllers with a specific goal in mind. So these controllers cannot be used in any other place.
Theoretically, an embedded controller is a combination of a piece of microprocessor based hardware and the suitable software to undertake a specific task.
These days designers have many choices in microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available variety really may overwhelm even an experienced designer. Selecting a right microprocessor may turn out as a most difficult first step and it is getting complicated as new devices continue to pop-up very often.

In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market acceptance of this particular family has driven many semiconductor manufacturers to develop something new based on this particular architecture. Even after 25 years of existence, semiconductor manufacturers still come out with some kind of device using this 8031 core.
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Communications applications

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LynuxWorks Jumpstart for Communications package enables OEMs to rapidly develop mission-critical communications equipment, with pre-integrated, state-of-the-art, data networking and porting software components”including source code for easy customization.
The Lynx Certifiable Stack (LCS) is a secure TCP/IP protocol stack designed especially for applications where standards certification is required.
Electronics applications and consumer devices

As the number of powerful embedded processors in consumer devices continues to rise, the BlueCat® Linux® operating system provides a highly reliable and royalty-free option for systems designers.
And as the wireless appliance revolution rolls on, web-enabled navigation systems, radios, personal communication devices, phones and PDAs all benefit from the cost-effective dependability, proven stability and full product life-cycle support opportunities associated with BlueCat embedded Linux. BlueCat has teamed up with industry leaders to make it easier to build Linux mobile phones with Java integration.
For makers of low-cost consumer electronic devices who wish to integrate the LynxOS real-time operating system into their products, we offer special MSRP-based pricing to reduce royalty fees to a negligible portion of the device's MSRP.
Industrial automation and process control software

Designers of industrial and process control systems know from experience that LynuxWorks operating systems provide the security and reliability that their industrial applications require.
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What is the difference between a Microprocessor and Microcontroller By microprocessor is meant the general purpose Microprocessors such as Intel's X86 family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010, 68020, 68030, 68040, etc). These microprocessors contain no RAM, no ROM, and no I/O ports on the chip itself. For this reason, they are commonly referred to as general-purpose Microprocessors.

A system designer using a general-purpose microprocessor such as the Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more expensive, they have the advantage of versatility such that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand. This is not the case with Microcontrollers.

A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip; therefore, the designer cannot add any external memory, I/O ports, or timer to it. The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical.
In many applications, for example a TV remote control, there is no need for the computing power of a 486 or even an 8086 microprocessor. These applications most often require some I/O operations to read signals and turn on and off certain bits.


In the Literature discussing microprocessors, we often see the term Embedded System. Microprocessors and Microcontrollers are widely used in embedded system products. An embedded system product uses a microprocessor (or Microcontroller) to do one task only. A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it. Contrast this with a Pentium based PC. A PC can be used for any number of applications such as word processor, print-server, bank teller terminal, Video game, network server, or Internet terminal. Software for a variety of applications can be loaded and run. Of course the reason a pc can perform myriad tasks is that it has RAM memory and an operating system that loads the application software into RAM memory and lets the CPU run it.

In an Embedded system, there is only one application software that is typically burned into ROM. An x86 PC contains or is connected to various embedded products such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on. Each one of these peripherals has a Microcontroller inside it that performs only one task. For example, inside every mouse there is a Microcontroller to perform the task of finding the mouse position and sending it to the PC. Table 1-1 lists some embedded products.

ARM Architecture

ARM Architecture

ARM History
ARM register file & modes of operation
Instruction Set

ARM History

The ARM (Acorn RISC Machine)architecture is developed at Acron Computer Limited of Cambridge, England between 1983-1985. ARM Limited founded in 1990. ARM became as the Advanced RISC Machine is a 32-bit RISC processor architecture that is widely used in embedded designs. ARM cores licensed to semiconductor partners who fabricate and sell to their customers. ARM does not fabricate silicon itself

Because of their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal. As of 2007, about 98 percent of the more than a billion mobile phones sold each year use at least one ARM CPU.
Today, the ARM family accounts for approximately 75% of all embedded 32-bit RISC CPUs, making it the most widely used 32-bit architecture. ARM CPUs are found in most corners of consumer electronics, from portable devices (PDAs, mobile phones, iPods and other digital media and music players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers).
ARM does not manufacture the CPU itself, but licenses it to other manufacturers to integrate them into their own system

ARM architecture

RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

History :
The first RISC project and implimentations came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors:
¢ one cycle execution time : RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ;
¢ pipelining : a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions;
¢ large number of registers : the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory


Price/Performance Strategies
Price: move complexity from software to hardware.
Performance: make tradeoffs in favor of decreased code size, at the expense of a higher CPI. Price: move complexity from hardware to software
Performance: make tradeoffs in favor of a lower CPI, at the expense of increased code size.
Design Decisions
¢ Execution of instructions takes many cycles
¢ Design rules are simple thus core operates at higher clock frequencies
¢ Memory-to-memory addressing modes.
¢ A microcode control unit.
¢ Spend fewer transistors on registers. ¢ Simple, single-cycle instructions that perform only basic functions. Assembler instructions correspond to microcode instructions on a CISC machine.
¢ Design rules are more complex and operates at lower clock frequencies
¢ Simple addressing modes that allow only LOAD and STORE to access memory. All operations are register-to-register.
¢ direct execution control unit.
¢ spend more transistors on multiple banks of registers.
¢ use pipelined execution to lower CPI.
Based upon RISC Architecture with enhancements to meet requirements of embedded applications ARM is having
1. A large uniform register file
2. Load-store architecture ,where data processing operations operate on register contents only
3. Uniform and fixed length instructions
4. 32 -bit processor
5. Instructions are 32-bit long
6. Good Speed/Power Consumption Ratio
7. High Code Density

Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both busses . Greater amount of instruction parallelism is possible in this architecture. Most DSPs use Harvard architecture for streaming data. The only difference in Harvard architecture to that of Von Neumann architecture is that the program and data memories are separated and use physically separate transmission paths . Enables the machine to transfer instructions and data simultaneously enhances performance. Harvard architecture is more commonly used in specialized microprocessors for real-time and embedded application. However, only the early DSP chips use the Harvard architecture because of the cost. The greatest disadvantage of the Harvard architecture is which needs twice as many address and data pins on the chips

A Von Neumann architecture store program and data in the same memory area with a single bus. So this bus only is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time. Most of the general-purpose microprocessors such as Motorola 68000 and Intel 80x86 use this architecture. It is simple in hardware implementation, but the data and program are required to share a single bus.

ARM Processor Core :
The figure shows the ARM core dataflow model. In which the ARM core as functional units connected by data buses,. And the arrows represent the flow of data, the lines represent the buses, and boxes represent either an operation unit or a storage area. The figure shows not only the flow of data but also the abstract components that make up an ARM core.
Fig : ARM core dataflow model

In the above figure the Data enters the processor core through the Data bus. The data may be an instruction to execute or a data item. This ARM core represents the Von Neumann implementation of the ARM data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two different buses.
The instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular instruction set.
The ARM processor ,like all RISC processors, use a load-store architecture. This means it has two instruction types for transferring data in and out of the processor : load instructions copy data from memory to registers in the core, and conversely the store instructions copy data from registers to memory. There are no data processing instructions that directly manipulate data in memory. Thus, data processing is carried out solely in registers.
Data items are placed in the register file “ a storage bank made up of 32-bit registers. Since the ARM core is a 32- bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values.
The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a register.
The ALU ( arithmetic logic unit ) or MAC ( multiply “ accumulate unit ) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and store instructions use the ALU to generate an address to be held in the address register and broadcast on the Address bus.
One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide range of expressions and addresses.
After passing through the functional units, the result in Rd is written back to the register file using the Result bus. For load and store instructions the incrementer updates the address register before the core reads or writes the next register value from or to the next sequential memory location. The processor continues executing instructions until an exception or interrupt changes the normal execution flow.

*ARM Bus Technology :
Embedded systems use different bus technologies. Most common PC bus technology is the Peripheral Component Interconnect ( PCI ) bus. Which connects devices such as video card and disk controllers to the X86 processor bus. This type of technology is called External or Off chip bus technology.
Embedded devices use an on-chip bus that is internal to the chip and allows different peripheral devices to be inter connected with an ARM core.
There are two different types of devices connected to the bus
1. Bus Master
2. Bus Slave
1. Bus Master : A logical device capable of initiating a data transfer with another device across the same bus (ARM processor core is a bus Master ).
2. Bus Slave : A logical device capable only of responding to a transfer request from a bus master device ( Peripherals are bus slaves )
Generally A Bus has two architecture levels
Physical lever : Which covers electrical characteristics an bus width (16,32,64 bus).
Protocol level : which deals with protocol
NOTE :- ARM is primarily a design company . It seldom implements the electrical characteristics of the bus , but it routinely specifies the bus protocol
AMBA (Advanced Microcontroller Bus Architecture )Bus protocol :
AMBA Bus was introduced in 1996 and has been widely adopted as the On Chip bus architecture used for ARM processors.
The first AMBA buses were
1. ARM System Bus ( ASB )
2. ARM Peripheral Bus ( APB )
Later ARM introduced another bus design called the ARM High performance Bus ( AHB )
Using AMBA
i. Peripheral designers can reuse the same design on multiple project and implimentations
ii. A Peripheral can simply be bolted on the On Chip bus with out having to redesign an interface for each different processor architecture.
This plug-and-play interface for hardware developers improves availability and time to market.
AHB provides higher data throughput than ASB because it is based on centralized multiplexed bus scheme rather than the ASB bidirectional bus design. This change allows the AHB bus to run at widths of 64 bits and 128 bits
ARM introduced two variations on the AHB bus
1. Multi-layer AHB
2. AHB-Lite
In contrast to the original AHB , which allows a single bus master to be active on the bus at any time , the Multi-layer AHB bus allows multiple active bus masters.
AHB-Lite is a subset of the AHB bus and it is limited to a single bus master. This bus was developed for designs that do not require the full features of the standard AHB bus.
AHB and Multiple-layer AHB support the same protocol for master and slave but have different interconnects. The new interconnects in Multi-layer AHB are good for systems with multiple processors. They permit operations to occur in parallel and allow for higher throughput rates.

Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation
The ISA has evolved to keep up with the demands of the embedded market. This evolution has been carefully managed by ARM , so that code written to execute on an earlier architecture revision will also execute on a later revision of the architecture.
The nomenclature identifies individual processors and provides basic information about the feature set.

ARM uses the nomenclature shown below is to describe the processor implementations.The letters and numbers after the word ARM indicate the features a processor may have.
ARM { x }{ y }{ z }{ T }{ D }{ M }{ I }{ E }{J }{ F }{ -S }
x family
y memory management / protection unit
z cache
T Thumb 16 bit decoder
D JTAG debug
M fast multiplier
I EmbeddedICE macrocell
E enhanced instruction ( assumes TDMI )
J Jazelle
F vector floating-point unit
S synthesizible version

All ARM cores after the ARM7TDMI include the TDMI features even though they may not include those letters after the ARM label
The processor family is a group of processor implementations that share the same hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all share the same family characteristics and belong to the ARM7 family
JTAG is described by IEEE 1149.1 standard Test Access Port and boundary scan architecture. It is a serial protocol used by ARM to send and receive debug information between the processor core and test equipment
EmbeddedICE macrocell is the debug hardware built into the processor that allows breakpoints and watchpoints to be set
Synthesizable means that the processor core is supplied as source code that can be compiled into a form easily used by EDA tools
Introduction to ARM7TDMI core
The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best combination of performance, power and area characteristics. The ARM7TDMI core enables system designers to build embedded devices requiring small size, low power and high performance.
ARM7TDMI Features
¢ 32/16-bit RISC architecture (ARM v4T)
¢ 32-bit ARM instruction set for maximum performance and flexibility
¢ 16-bit Thumb instruction set for increased code density
¢ Unified bus interface, 32-bit data bus carries both instructions and data
¢ Three-stage pipeline
¢ 32-bit ALU
¢ Very small die size and low power consumption
¢ Fully static operation
¢ Coprocessor interface
¢ Extensive debug facilities (EmbeddedICE debug unit accessible via JTAG interface unit)
¢ Generic layout can be ported to specific process technologies
¢ Unified memory bus simplifies SoC integration process
¢ ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
¢ Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7 Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's quite easy to port your design to higher level microcontroller or microprocessor
¢ Static design and lower power consumption are essential for battery -powered devices
¢ Instruction set can be extended for specific requirements using coprocessors
¢ EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities

ARM7TDMI Microcontrollers
1. Available ARM7TDMI Microcontrollers
2. Analog Devices ADuC 7xxx
3. Atmel AT91SAM7
4. Freescale MAC7100
5. NXP/Philips LPC2000
6. ST STR710
7.Texas Instruments TMS470

2.3 ARM Register file & modes of operation

Registers : General Purpose registers hold either data or address they are identified with the letter r prefixed to the register number. All registers are of 32 bits.
ARM has 37 registers in total, all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access a particular set of r0-r12 registers, a particular r13 (the stack pointer) and r14 (link register), r15 (the program counter), cpsr (the current program status register)
and privileged modes can also access a particular spsr (saved program status register).
In user mode 16 data registers and 2 status registers are visible. Depending upon context, register r13 and r14 can also be used as General Purpose Registers. In ARM state the registers r0 to r13 are Orthogonal that means - any instruction which use r0 can as well be used with any other General Purpose Register (r1-r13).
The ARM processor has three registers assigned to a particular task or special function: r13,r14 and r15. They are frequently given different labels to differentiate them from the other registers.
Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack in the current processor mode
Register r14 is called the link register ( lr ) and is where the core puts the return address whenever it calls a subroutine.
Register r15 is the program counter ( pc ) and contains the address of the next instruction to be fetched by the processor
The register file contains all the registers available to a programmer. Which registers are visible to the programmer depend upon the current mode of the processor.
Current program status register :
The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated 32-bit register and resides in the register file. The following figure shows the generic program status register.

Fig: Program Status Register

The control bit field contains the processor mode, state , and interrupt mask bits (I,F). Reserved bits are allocated for the future versions purpose.
The N, Z, C and V are condition code flags will be changed as a result of arithmetic and logical operations in the processor
N : Negative. Z : Zero. C : Carry. V : Overflow
The I and F bits are the interrupt disable bits
The M0, M1, M2, M3 and M4 bits are the mode bits
Processor Modes: Processor modes determine which register are active, and access rights to CPSR register itself. Each processor mode is either Privileged or Non-privileged. ARM has seven modes. These 7 modes are divided into two types.

Privileged :- Full read-write access to the CPSR. Under this we are having Abort, Fast interrupt request, Interrupt request, Supervisor,System and Undefined
Abort (10111) :
when there is a failed attempt to access memory
Fast interrupt Request (FIQ(10001)) & interrupt request(10010) :
correspond to interrupt levels available on ARM
Supervisor mode(10011) :
state after reset and generally the mode in which OS kernel executes
System mode(11111) :
special version of user mode that allows full read-write access of CPSR
Undefined(11011) :
when processor encounters an undefined instruction
Non-privileged :- Only read access to the control filed of CPSR but read-write access to the condition flags.
User(10000): User mode is user for programs and applications. And this the normal mode

Banked Registers :
Register file contains in all 37 registers. 20 registers are hidden from program at different times. These registers are called banked registers. Banked registers are available only when the processor is in a particular mode. Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 register

Each privileged mode (except system mode) has associated with it a Save Program Status Register, or SPSR. This SPSR is used to save the state of CPSR (Current program status Register) when the privileged mode is entered in order that the user state can be fully restored when the user processor is resumed

Mode Changing :
Mode changes by writing directly to CPSR or by hardware when the processor responds to exception or interrupt
To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers

ARM Instruction Set
In this chapter we are going to discuss about the most commonly used Instruction Set of ARM. Different ARM architectures revisions support different instructions. However new revisions usually add instructions and remain backwardly compatible. The following shows the type of instructions that ARM support.
I. Data Processing Instructions
II. Branch Instructions
III. Load-store Instructions
IV. Software Interrupt Instruction
V. Program Status Register Instructions

I. Data Processing Instructions :-
The data processing instructions manipulate data within registers. Most data processing instructions can process one of their operands using the barrel shifter. If we use the S suffix on a data processing instruction, then it updates the flags in the cpsr. Move and logical operations update the carry flag C, negative flag N, and Zero flag Z. The carry flag is set from the result of the barrel shift as the last bit shifted out. The N flag is set to bit 31 of the result. The Z flag is set if the result is zero. The following instructions are Data processing instructions.
i). Move instructions: This instruction is used to move the content of one register to another register. The below instructions are the Move instructions
MOV : move a 32-bit value into a register Rd=RS
MOVN : move the NOT of the 32 bit value into a register Rd= ~RS

ii). Barrel Shifter :- A unique and powerful feature of ARM processor is ability to shift the 32-bit binary pattern in one of the source registers left or right by a specific number of positions before it enters the ALU. This is done by using the Barrel shifter. This preprocessing or shift occurs within the cycle time of the instruction. The five different shift operations that we can use within the barrel shifter given below.
LSL : logical shift left
LSR : logical shift right
ASR : arithmetic right shift
ROR : rotate right
RRX : rotate right extended

iii. Arithmetic Instructions : The arithmetic instructions implement and subtraction of 32-bit signed and unsigned values. Some of the instructions of Arithmetic instructions are given below.
ADD :add two 32-bit values.
ADC :add two 32-bit values and carry
SUB Confusedubtract two 32-bit values
SBC : subtract with carry of two 32-bit values
RSB : reverse subtract of two 32-bit values
RSC : reverse subtract with carry of two 32-bit values

iv. Logical Instructions : Performs the logical operations on two source registers
AND : logical bitwise AND of two 32-bit values
ORR : logical bitwise OR of two 32-bit values
EOR : logical exclusive OR of two 32-bit vlaues.
BIC : Logical bit clear (AND NOT)

v. Comparison Instructions : The comparison instructions are used to compare or test a register with a 32 bit value. They update the cpsr flag bits (N, Z, C, V) according to the result, but do not affect other registers. After the bits have been set, the information can then be used to change program flow by using conditional execution. We do not need to apply the S suffix for comparison instructions to update the flag. The following instructions are belong Comparison instructions
CMP (compare) : flags set as a result of R1-R2
CMN (compare negated) : flags set as a result of R1+R2
TST (test for equality of two 32-bit values) : flags set as a result of R1&R2
TEQ (test for equality of two 32-bit values) : flags set as a result of R1^R2

vi. Multiply Instructions : The multiply instructions multiply the content of a pair of registers and , depending upon the instruction, accumulate the results in with another register. The long multiplies accumulate onto a pair of registers representing a 64 bit value. The final result is placed in a destination register or a pair of registers.
MUL : multiply
MLA : multiply and accumulate

Long Multiply Instructions : (Produce 64 bit values,result will be placed in two 32 bit values)
SMLAL : signed multiply accumulate long
SMULL : signed multiply accumulate
UMLAL : unsigned multiply accumulate long
UMULL : unsigned multiply long

II. Branch Instructions :- A branch instruction changes the flow of execution or is used to call a routine. This type of instruction allows programs to have subroutines, if-then-else structures, and loops. The change of execution flow forces the program counter pc to point to new address. The below shown instructions are Branch instructions.
B : branch
BL : branch with link
BX : branch exchange
BLX : branch exchange with link

III. Load-store Instructions :- Load-store instructions transfer data between memory and processor registers.
There are three types of load-store instructions :
i. single register transferring
ii. Multiple register transfer
iii. Swap

Single register transferring :- These instructions are used for moving a single data item in and out of a register. The data types supported are signed and unsigned words(32-bit), halfwords(16-bit), and bytes. The following instructions are various load-store single-register transfer instructions.
LDR : load word into a register
STR : save byte or word from a register
LDRB : load byte into a register
STRB : save byte from a register
LDRH : load halfword into a register
STRH : save halfword into a register
LDRSB : load signed byte into a register
LDRSH : load signed halfword into a register

Multiple register transfer : - Load-store multiple instructions can transfer multiple registers between memory and the processor in a single instruction. The transfer occurs from a base address register Rn pointing into memory. Multiple-register transfer instructions are more efficient from single-register transfers for moving blocks of data around memory and saving and restoring context and stacks. If an interrupt has been raised, then it has no effect until the load-store multiple instruction is complete.
LDM : load multiple registers
STM : save multiple registers

Swap :- The swap instruction is a special case of a load-store instruction. It swaps the contents of memory with the contents of a register. This instruction is an atomic operation- it reads and writes a location in the same bus operation, preventing any other instruction from reading or writing to that location until it completes.

IV. Software Interrupt Instruction :- A software interrupt instruction ( SWI ) causes a software interrupt exception, which provides a mechanism for applications to call operating system routines. The following instruction comes under software interrupt instruction.
SWI : software interrupt
V. Program Status Register Instructions :- The ARM instruction set provides two instructions to directly control a program status ( psr ).
MRS : This instruction transfers the contents of either the cpsr or spsr into a register
MSR : This instruction transfers the content of a register into the cpsr or spsr

Together the above two instructions are used to read and write the cpsr or spsr



General description of LPC 2148:
The LPC2148 microcontrollers is based on a 32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine microcontrollers with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb
mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADCs, 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems.

General overview of in system programming (ISP):

In-System Programming (ISP) is a process whereby a blank device mounted to a circuit board can be programmed with the end-user code without the need to remove the device from the circuit board. Also, a previously programmed device can be erased and Re programmed without removal from the circuit board. In order to perform ISP operations the microcontroller is powered up in a special ISP mode. ISP mode allows the microcontroller to communicate with an external host device through the serial port, such as a PC or terminal. The microcontroller receives commands and data from the host, erases and reprograms code memory, etc. Once the ISP operations have been completed the device is reconfigured so that it will operate normally the next time it is either reset or power removed and reapplied. All of the Philips microcontrollers shown in Table 1 and Table 2 have a 1 kbyte factory-masked ROM located in the upper 1 kbyte of code memory space from FC00 to FFFF. This 1 kbyte ROM is in addition to the memory blocks shown in Table 1 and Table 2. This ROM is referred to as the Bootrom. This Bootrom contains a set of instructions which allows the microcontroller to perform a number of Flash programming and erasing functions. The Bootrom also provides communications through the serial port. The use of the Bootrom is key to the concepts of both ISP and In-Application Programming (IAP). The contents of the bootrom are provided by Philips and masked into every device. When the device is reset or power applied, and the EA/ pin is high or at the VPP voltage, the microcontroller will start executing instructions from either the user code memory space at address 0000h (normal mode) or will execute instructions from the Bootrom (ISP mode).


Some applications may have a need to be able to erase and program code memory under the control fo the application. For example, an application may have a need to store calibration information or perhaps need to be able to download new code portions. This ability to erase and program code memory in the end-user application is In-Application Programming (IAP). The Bootrom routines which perform functions on the Flash memory during ISP mode such as programming, erasing, and reading, are also available to end-user programs. Thus it is possible for an end-user application to perform operations on the Flash memory. A common entry point (FFF0h) to these routines has been provided to simplify interfacing to the end-users application. Functions are performed by setting up specific registers as required by a specific operation and performing a call to the common entry point. Like any other subroutine call, after completion of the function, control will return to the end-userâ„¢s code. The Bootrom is shadowed with the user code memory in the address range from FC00h to FFFFh. This shadowing is controlled by the ENBOOT bit (AUXR1.5). When set, accesses to internal code memory in this address range will be from the boot ROM. When cleared, accesses will be from the userâ„¢s code memory. It will be NECESSARY for the end-userâ„¢s code to set the ENBOOT bit prior to calling the common entry point for IAP operations, even for devices with 16 kbyte, 32 kbyte, and 64 kbyte of internal code memory. (ISP operation is selected by certain hardware conditions and control of the ENBOOT bit is automatic when ISP mode is activated).

Key features:

16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package
8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory; 128-bit wide interface/accelerator enables high-speed 60 MHz operation
In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software, single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms.
Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high-speed tracing of instruction execution
USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM
In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA
One or two (LPC2141/42 vs, LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 ms per channel Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only)
Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities
Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package
Up to 21 external interrupt pins available
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 ms
On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz
Power saving modes include Idle and Power-down
Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization
Processor wake-up from Power-down mode via external interrupt or BOD
Single power supply chip with POR and BOD circuits:
CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.



Pin Description:

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block.


P0.0 ” General purpose input/output digital pin (GPIO)
TXD0 ” Transmitter output for UART0
PWM1 ” Pulse Width Modulator output 1


P0.1 ” General purpose input/output digital pin (GPIO)
RXD0 ” Receiver input for UART0
PWM3 ” Pulse Width Modulator output 3
EINT0 ” External interrupt 0 input

P0.2/SCL0/ CAP0.0:

P0.2 ” General purpose input/output digital pin (GPIO)
SCL0 ” I2C0 clock input/output, open-drain output (for I2C-bus compliance)
CAP0.0 ” Capture input for Timer 0, channel 0
P0.3/SDA0/ MAT0.0/EINT1:

P0.3 ” General purpose input/output digital pin (GPIO)
SDA0 ” I2C0 data input/output, open-drain output (for I2C-bus compliance)
MAT0.0 ” Match output for Timer 0, channel 0
EINT1 ” External interrupt 1 input

P0.4/SCK0/ CAP0.1/AD0.6

P0.4 ” General purpose input/output digital pin (GPIO)
SCK0 ” Serial clock for SPI0, SPI clock output from master or input to slave
CAP0.1 ” Capture input for Timer 0, channel 0
AD0.6 ” ADC 0, input 6.

P0.5/MISO0/ MAT0.1/AD0.7

P0.5 ” General purpose input/output digital pin (GPIO)
MISO0 ” Master In Slave OUT for SPI0, data input to SPI master or data output from
SPI slave.
MAT0.1 ” Match output for Timer 0, channel 1
AD0.7 ” ADC 0, input 7

P0.6/MOSI0/ CAP0.2/AD1.0

P0.6 ” General purpose input/output digital pin (GPIO)

MOSI0 ” Master out Slave In for SPI0, data output from SPI master or data
Input to SPI slave
CAP0.2 ” Capture input for Timer 0, channel 2
AD1.0 ” ADC 1, input 0, available in LPC2144/46/48 only


P0.7 ” General purpose input/output digital pin (GPIO)
SSEL0 ” Slave Select for SPI0, selects the SPI interface as a slave
PWM2 ” Pulse Width Modulator output 2
EINT2 ” External interrupt 2 input

P0.8 ” General purpose input/output digital pin (GPIO)
TXD1 ” Transmitter output for UART1
PWM4 ” Pulse Width Modulator output 4
AD1.1 ” ADC 1, input 1, available in LPC2144/46/48 only

P0.9/RXD1/ PWM6/EINT3:

P0.9 ” General purpose input/output digital pin (GPIO)
RXD1 ” Receiver input for UART1
PWM6 ” Pulse Width Modulator output 6
EINT3 ” External interrupt 3 input
P0.10/RTS1/ CAP1.0/AD1.2:

P0.10 ” General purpose input/output digital pin (GPIO)
RTS1 ” Request to send output for UART1, LPC2144/46/48 only
CAP1.0 ” Capture input for Timer 1, channel 0
AD1.2 ” ADC 1, input 2, available in LPC2144/46/48 only

P0.11/CTS1/ CAP1.1/SCL1:

P0.11 ” General purpose input/output digital pin (GPIO)
CTS1 ” Clear to send input for UART1, available in LPC2144/46/48 only
CAP1.1 ” Capture input for Timer 1, channel 1
SCL1 ” I2C1 clock input/output, open-drain output (for I2C-bus compliance)


P0.12 ” General purpose input/output digital pin (GPIO)
DSR1 ” Data Set Ready input for UART1, available in LPC2144/46/48 only
MAT1.0 ” Match output for Timer 1, channel 0
AD1.3 ” ADC input 3, available in LPC2144/46/48 only

P0.13/DTR1/ MAT1.1/AD1.4:

P0.13 ” General purpose input/output digital pin (GPIO)
DTR1 ” Data Terminal Ready output for UART1, LPC2144/46/48 only
MAT1.1 ” Match output for Timer 1, channel 1
AD1.4 ” ADC input 4, available in LPC2144/46/48 only


P0.14 ” General purpose input/output digital pin (GPIO)
DCD1 ” Data Carrier Detect input for UART1, LPC2144/46/48 only
EINT1 ” External interrupt 1 input
SDA1 ” I2C1 data input/output, open-drain output (for I2C-bus compliance LOW on this pin while RESET is LOW forces on-chip boot loader to take over control of the part after reset

P0.15/RI1/ EINT2/AD1.5:

P0.15 ” General purpose input/output digital pin (GPIO)
RI1 ” Ring Indicator input for UART1, available in LPC2144/46/48 only
EINT2 ” External interrupt 2 input
AD1.5 ” ADC 1, input 5, available in LPC2144/46/48 only


P0.16 ” General purpose input/output digital pin (GPIO)
EINT0 ” External interrupt 0 input
MAT0.2 ” Match output for Timer 0, channel 2
CAP0.2 ” Capture input for Timer 0, channel 2
P0.17/CAP1.2/ SCK1/MAT1.2:

P0.17 ” General purpose input/output digital pin (GPIO)
CAP1.2 ” Capture input for Timer 1, channel 2
SCK1 ” Serial Clock for SSP, clock output from master or input to slave
MAT1.2 ” Match output for Timer 1, channel 2


P0.18 ” General purpose input/output digital pin (GPIO)
CAP1.3 ” Capture input for Timer 1, channel 3
MISO1 ” Master In Slave Out for SSP, data input to SPI master or data output from SSP slave
MAT1.3 ” Match output for Timer 1, channel 3


P0.19 ” General purpose input/output digital pin (GPIO)
MAT1.2 ” Match output for Timer 1, channel 2
MOSI1 ” Master out Slave In for SSP, data output from SSP master or data Input to SSP slave
CAP1.2 ” Capture input for Timer 1, channel 2


P0.20 ” General purpose input/output digital pin (GPIO)
MAT1.3 ” Match output for Timer 1, channel 3
SSEL1 ” Slave Select for SSP, selects the SSP interface as a slave
EINT3 ” External interrupt 3 input


P0.21 ” General purpose input/output digital pin (GPIO)
PWM5 ” Pulse Width Modulator output 5
AD1.6 ” ADC 1, input 6, available in LPC2144/46/48 only
CAP1.3 ” Capture input for Timer 1, channel 3


P0.22 ” General purpose input/output digital pin (GPIO)
AD1.7 ” ADC 1, input 7, available in LPC2144/46/48 only
CAP0.0 ” Capture input for Timer 0, channel 0
MAT0.0 ” Match output for Timer 0, channel 0

P0.23 ” General purpose input/output digital pin (GPIO)
VBUS ” Indicates the presence of USB bus power
This signal must be HIGH for USB reset to occur


P0.25 ” General purpose input/output digital pin (GPIO)
AD0.4 ” ADC 0, input 4
AOUT ” DAC output, available in LPC2142/44/46/48 only

P0.28 ” General purpose input/output digital pin (GPIO)
AD0.1 ” ADC 0, input 1
CAP0.2 ” Capture input for Timer 0, channel 2
MAT0.2 ” Match output for Timer 0, channel 2


P0.29 ” General purpose input/output digital pin (GPIO)
AD0.2 ” ADC 0, input 2
CAP0.3 ” Capture input for Timer 0, Channel 3
MAT0.3 ” Match output for Timer 0, channel 3


P0.30 ” General purpose input/output digital pin (GPIO)
AD0.3 ” ADC 0, input 3
EINT3 ” External interrupt 3 input
CAP0.0 ” Capture input for Timer 0, channel 0


P0.31 ” General purpose output only digital pin (GPO)
UP_LED ” USB Good Link LED indicator, it is LOW when device is configured (non-control endpoints enabled), it is HIGH when the device is not configured or during global suspend
CONNECT ” Signal used to switch an external 1.5 kohms resistor under the
Software control, used with the Soft Connect USB feature
Important: This is a digital output only pin, this pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit, the operation of port 1 pins depends upon the pin function selected via the pin connect block, pins 0 through 15 of port 1 are not


P1.16 ” General purpose input/output digital pin (GPIO)
TRACEPKT0 ” Trace Packet, bit 0, standard I/O port with internal pull-up


P1.17 ” General purpose input/output digital pin (GPIO)
TRACEPKT1 ” Trace Packet, bit 1, standard I/O port with internal pull-up


P1.18 ” General purpose input/output digital pin (GPIO)
TRACEPKT2 ” Trace Packet, bit 2, standard I/O port with internal pull-up


P1.19 ” General purpose input/output digital pin (GPIO)
TRACEPKT3 ” Trace Packet, bit 3, standard I/O port with internal pull-up


P1.20 ” General purpose input/output digital pin (GPIO)
TRACESYNC ” Trace Synchronization, standard I/O port with internal pull-up
Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset


P1.21 ” General purpose input/output digital pin (GPIO)
PIPESTAT0 ” Pipeline Status, bit 0, standard I/O port with internal pull-up


P1.22 ” General purpose input/output digital pin (GPIO)
PIPESTAT1 ” Pipeline Status, bit 1, standard I/O port with internal pull-up


P1.23 ” General purpose input/output digital pin (GPIO)
PIPESTAT2 ” Pipeline Status, bit 2, standard I/O port with internal pull-up


P1.24 ” General purpose input/output digital pin (GPIO)
TRACECLK ” Trace Clock, standard I/O port with internal pull-up


P1.25 ” General purpose input/output digital pin (GPIO)
EXTIN0 ” External Trigger Input, standard I/O with internal pull-up


P1.26 ” General purpose input/output digital pin (GPIO)
RTCK ” Returned Test Clock output, extra signal added to the JTAG port, assists debugger synchronization when processor frequency varies, bidirectional pin with internal pull-up
Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate a Debug port after reset


P1.27 ” General purpose input/output digital pin (GPIO)
TDO ” Test Data out for JTAG interface


P1.28 ” General purpose input/output digital pin (GPIO)
TDI ” Test Data in for JTAG interface


P1.29 ” General purpose input/output digital pin (GPIO)
TCK ” Test Clock for JTAG interface


P1.30 ” General purpose input/output digital pin (GPIO)
TMS ” Test Mode Select for JTAG interface


P1.31 ” General purpose input/output digital pin (GPIO)
TRST ” Test Reset for JTAG interface

D+: USB bidirectional D+ line

D- : USB bidirectional D- line

RESET External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0, TTL with hysteretic, 5 V tolerant

XTAL1: Input to the oscillator circuit and internal clock generator circuits
XTAL2: Output from the oscillator amplifier
RTCX1: I Input to the RTC oscillator circuit
RTCX2: Output from the RTC oscillator circuit

VSS: 6, 18, 25, 42, 50 pins are for supply voltage.

Ground: 0 V reference.

VSSA Analog ground: 0 V reference, this should nominally be the same voltage as
VSS, but should be isolated to minimize noise and error

VDD 23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O ports.

VDDA 7 I Analog 3.3 V power supply: This should be nominally the same voltage as
VDD but should be isolated to minimize noise and error, this voltage is only used to power the on-chip ADC(s) and DAC

VREF ADC reference voltage: This should be nominally less than or equal to the
VDD voltage but should be isolated to minimize noise and error, level on this
Pin is used as a reference for ADC(s) and DAC

VBAT RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC.
Functional Description:

Architectural Overview:
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
And impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set.

Essentially, the ARM7TDMI-S processor has two instruction sets:
¢ The standard 32-bit ARM set
¢ A 16-bit Thumb set

The Thumb setâ„¢s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMâ„¢s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode.
On-Chip Flash Program memory:

The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for userâ„¢s code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.

The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention.
On-Chip Static RAM:

On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution.

Memory Map:

The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown below.

Interrupt controller:

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast interrupt request (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.

Interrupt Sources:
Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Pin Connect Block:

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undef
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Fast General purpose Parallel I/O:
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow the setting or clearing of any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2141/42/44/46/48 introduces accelerated GPIO functions over prior LPC2000 devices:

¢ GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing
¢ Mask registers allow treating sets of port bits as a group, leaving other bits unchanged
¢ All GPIO registers are byte addressable
¢ Entire port value can be written in one instruction

¢ Bit-level set and clear registers allow a single instruction to set or clear any number of bits in one port
¢ Direction control of individual bits
¢ Separate control of output set and clear
¢ All I/O default to inputs after reset
10 bit ADC:
The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.
10 bit DAC:
The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage.
USB 2.0 Device controller:

The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. The host controller allocates the USB bandwidth to
Attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller.

The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM.

The LPC2141/42/44/46/48 each contains two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provide a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in LPC2144/46/48 only).
I2C Bus Serial I/O Controller

The LPC2141/42/44/46/48 each contains two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus; it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus).

SPI Serial I/O Controller:

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.

SSP Serial I/O Controller

The LPC2141/42/44/46/48 each contains one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Micro wire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data.
General Purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signals transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with Ëœorâ„¢ and Ëœandâ„¢, as well as Ëœbroadcastâ„¢ functions among them. The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts.

Watchdog Timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to Ëœfeedâ„¢ (or reload) the watchdog within a predetermined amount of time.
Real Time Clock:
The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
Pulse width modulator
The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.

Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two matches registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

System Control

1. Crystal Oscillator:

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected.
2. PLL:
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 ms.

3. Reset and Wake up Timer:

Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

4. Brown out Detector

The LPC2141/42/44/46/48 includes 2-stage monitoring of the voltage on the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register.

The second stage of low voltage detection asserts reset to inactivate the LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition.

5. Code Security

This feature of the LPC2141/42/44/46/48 allows an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase using the ISP.

6. External Interrupt Inputs:

The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode.

7. Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.

8. Power Control

The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and
Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and Idle mode.

The VPB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first is to provide peripherals with the desired PCLK via VPB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be slowed down to 1¤2 to 1¤4 of the processor clock rate. Because the VPB bus must work properly at power-up (and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at 1¤4 of the processor clock rate. The second purpose of the VPB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the VPB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
10. Emulation and Debugging:

The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port0 are available during the development and debugging phase as they are when the application is run in the embedded system
11. Embedded ICE

Standard ARM Embedded ICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an Embedded ICE protocol converter. Embedded ICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the Embedded ICE logic.

12. Embedded Trace:

Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macro cell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.

13. Real Monitor:

Real Monitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the Embedded ICE logic. The LPC2141/42/44/46/48 contains a specific configuration of Real Monitor software programmed into the on-chip flash memory




Radio frequency identification is a powerful emerging technology that enables companies to achieve total business visibility. By knowing the identity, location and conditions of assets, tools, inventory, people and more, companies can optimize business processes and reduce operational costs. Radio frequency identification (RFID) is a generic term that is used to describe a system that transmits the identity (in the form of a unique serial number) of an object or person wirelessly, using radio waves.

RFID reader module, are also called as interrogators. They convert radio waves returned form the RFID tag into a form that can be pressed on to controllers, which can make use of it. RFID tags and readers have to be tuned to the same frequency in order to communicate. RFID systems use many different frequencies, but the most common and widely used and supported by our Reader 125 KHz.

An RFID reader typically contains a module (transmitter and receiver), a control unit and a coupling element (antenna). The reader has three main functions: energizing, demodulating and decoding. In addition, readers can be fitted with an additional interface that converts the radio waves returned from the RFID tag into a form that can then be passed on to another system, like a computer or any programmable logic controller. Anti-Collision algorithms permit the simultaneous reading of large numbers of tagged objects, while ensuring that each tag is read only once.




A basic RFID system consists of three components:

¢ An antenna or coil
¢ A transceiver (with decoder)
¢ A transponder (RF tag) electronically programmed with unique information.

The antenna emits radio signals to activate the tag and read and write data to it. Antennas are available in a variety of shapes and sizes; they can be built into a doorframe to receive tag data from persons or things passing through the door, or mounted on an interstate tollbooth to monitor traffic passing by on a freeway. Antennas can also be mounted on mobile devices and under print heads.

Often the antenna is packaged with the transceiver and decoder to become a reader (a.k.a. interrogator), which can be configured either as a handheld or a fixed-mount device. The reader emits radio waves in ranges of anywhere from one inch to 100 feet or more, depending upon its power output and the radio frequency used. When an RFID tag passes through the electromagnetic zone, it detects the readerâ„¢s activation signal. The reader decodes the data encoded in the tagâ„¢s integrated circuit (silicon chip) and the data is passed to the host computer for processing.

The purpose of an RFID system is to enable data to be transmitted by a portable device, called a tag, which is read by an RFID reader and processed according to the needs of a particular application. The data transmitted by the tag may provide identification or location information, or specifics about the product tagged, such as price, color, date of purchase, etc. RFID technology has been used by thousands of companies for a decade or more. . RFID quickly gained attention because of its ability to track moving objects. As the technology is refined, more pervasive - and invasive - uses for RFID tags are in the works.
A typical RFID tag consists of a microchip attached to a radio antenna mounted on a substrate. The chip can store as much as 2 kilobytes of data.

To retrieve the data stored on an RFID tag, you need a reader. A typical reader is a device that has one or more antennas that emit radio waves and receive signals back from the tag. The reader then passes the information in digital form to a computer system.

More About Antennas

Antennas are the conduits between the tag and the transceiver, which controls the system's data acquisition and communication. Antennas are available in a variety of shapes and sizes; they can be built into a door frame to receive tag data from persons or things passing through the door, or mounted on an interstate toll booth to monitor traffic passing by on a freeway. The electromagnetic field produced by an antenna can be constantly present when multiple tags are expected continually. If constant interrogation is not required, the field can be activated by a sensor device.
Often the antenna is packaged with the transceiver and decoder to become a reader (a.k.a. interrogator), which can be configured either as a handheld or a fixed-mount device.
RFID tags come in a wide variety of shapes and sizes. Animal tracking tags, inserted beneath the skin, can be as small as a pencil lead in diameter and one-half inch in length. Tags can be screw-shaped to identify trees or wooden items, or credit-card shaped for use in access applications. The anti-theft hard plastic tags attached to merchandise in stores are RFID tags. In addition, heavy-duty 5- by 4- by 2-inch rectangular transponders used to track intermodal containers or heavy machinery, trucks, and railroad cars for maintenance and tracking applications are RFID tags.

There are a variety of RFID tag types. Selecting the correct tag will be imperative to ensure a proper functioning system. Selecting the proper tag will be discussed later. Tags can be placed on wooden or plastic pallets, clothing, embedded into traditional barcode labels, animals, metal surfaces, and much more.

A tag is comprised of:

¢ Silicon chip: Integrated circuit (IC chip) that contains the data.
¢ Antenna: An antenna is attached to the chip in order to receive and transmit its data.
¢ Substrate: This is the paper or plastic film or housing that the chip and antenna are mounted on.

The data associated with a tag is programmed into the chip. The tag is placed on merchandise and is activated and read when it is energized by the reader and antenna system.

The IC contains an actual microchip where data is stored. Chips are available in many sizes and configurations. They can be extremely small to be incorporated into small form factor RFID tags. The chips' capability to carry data and have that data amended is defined by their Read/Write characteristics.

An RFID tag can take on many form factors and power levels. The unique identifier is encoded onto the integrated circuit and travels with this data. The data on the RFID IC is transmitted to a reader through the antenna incorporated onto the tag. RFID tags can be as tiny as an ant's head, larger than the palm of an adult hand, or any size in between. The form factor that the RFID tag takes is dictated by factors including power, durability, and lifetime requirements. Tag characteristics are defined by the application, and can vary in power requirements, read/write capability, and frequency. RFID tags are developed using a frequency according to the needs of the system including read range and the environment in which the tag will be read.

Active or Passive RFID ¦

RFID tags are categorized as either active or passive. Active RFID tags are powered by an internal battery and are typically read/write, i.e., tag data can be rewritten and/or modified. An active tag's memory size varies according to application requirements; some systems operate with up to 1MB of memory. In a typical read/write RFID work-in-process system, a tag might give a machine a set of instructions, and the machine would then report its performance to the tag. This encoded data would then become part of the tagged part's history. The battery-supplied power of an active tag generally gives it a longer read range. The trade off is greater size, greater cost, and a limited operational life (which may yield a maximum of 10 years, depending upon operating temperatures and battery type).
Passive RFID tags operate without a separate external power source and obtain operating power generated from the reader. Passive tags are consequently much lighter than active tags, less expensive, and offer a virtually unlimited operational lifetime. The trade off is that they have shorter read ranges than active tags and require a higher-powered reader. Read-only tags are typically passive and are programmed with a unique set of data (usually 32 to 128 bits) that cannot be modified. Read-only tags most often operate as a license plate into a database, in the same way as linear barcodes reference a database containing modifiable product-specific information.
RFID systems are also distinguished by their frequency ranges.
¢ Low-frequency or LF (30 KHz to 500 KHz) systems have short reading ranges and lower system costs. They are most commonly used in security access, asset tracking, and animal identification applications.
¢ High-frequency or HF (850 MHz to 950 MHz and 2.4 GHz to 2.5 GHz) systems, offering long read ranges (greater than 90 feet) and high reading speeds, are used for such applications as railroad car tracking and automated toll collection. However, the higher performance of high-frequency RFID systems incurs higher system costs.
¢ Ultra high frequency or UHF
The significant advantage of all types of RFID systems is the noncontact, non-line-of-sight nature of the technology. Tags can be read through a variety of substances such as snow, fog, ice, paint, crusted grime, and other visually and environmentally challenging conditions, where bar codes or other optically read technologies would be useless. RFID tags can also be read in challenging circumstances at remarkable speeds, in most cases responding in less than 100 milliseconds. The read/write capability of an active RFID system is also a significant advantage in interactive applications such as work-in-process or maintenance tracking. Though it is a costlier technology (compared with bar code), RFID has become indispensable for a wide range of automated data collection and identification applications that would not be possible otherwise.
Developments in RFID technology continue to yield larger memory capacities, wider reading ranges, and faster processing. It is highly unlikely that the technology will ultimately replace bar code ” even with the inevitable reduction in raw materials coupled with economies of scale, the integrated circuit in an RF tag will never be as cost-effective as a barcode label. However, RFID will continue to grow in its established niches where bar code or other optical technologies are not effective.

Inventory efficiency - Because line of sight is not required to read RFID tags, inventory can be performed in a highly efficient method. For example, pallets in a warehouse can be read, inventoried, and their location can be determined no matter where the tag is placed on the pallet. This is because the radio waves from the reader are strong enough for the tag to respond regardless of location.

Return on investment - Though the cost may be high at first, the total cost of ownership should go down over the years and provide a return on investment (ROI), if the implementation provides a significant method to improve business processes.
Vulnerability to damage minimized - barcodes can be damaged in many ways. Although, 2D barcode types such as Data Matrix can be read even when up to 40% of the barcode is damaged.


A relay is an electrical switch that opens and closes under the control of another electrical circuit. In the original form, the switch is operated by an electromagnet to open or close one or many sets of contacts. Because a relay is able to control an output circuit of higher power than the input circuit, it can be considered to be, in a broad sense, a form of an electrical amplifier.
Small relay as used in electronics
A simple electromagnetic relay, such as the one taken from a car in the first picture, is an adaptation of an electromagnet. It consists of a coil of wire surrounding a soft iron core, an iron yoke, which provides a low reluctance path for magnetic flux, a moveable iron armature, and a set, or sets, of contacts; two in the relay pictured. The armature is hinged to the yoke and mechanically linked to a moving contact or contacts. It is held in place by a spring so that when the relay is de-energised there is an air gap in the magnetic circuit. In this condition, one of the two sets of contacts in the relay pictured is closed, and the other set is open. Other relays may have more or fewer sets of contacts depending on their function. The relay in the picture also has a wire connecting the armature to the yoke. This ensures continuity of the circuit between the moving contacts on the armature, and the circuit track on the Printed Circuit Board (PCB) via the yoke, which is soldered to the PCB.
When an electric current is passed through the coil, the resulting magnetic field attracts the armature, and the consequent movement of the movable contact or contacts either makes or breaks a connection with a fixed contact. If the set of contacts was closed when the relay was de-energised, then the movement opens the contacts and breaks the connection, and vice versa if the contacts were open. When the current to the coil is switched off, the armature is returned by a force, approximately half as strong as the magnetic force, to its relaxed position. Usually this force is provided by a spring, but gravity is also used commonly in industrial motor starters. Most relays are manufactured to operate quickly. In a low voltage application, this is to reduce noise. In a high voltage or high current application, this is to reduce arcing.
If the coil is energized with DC, a diode is frequently installed across the coil, to dissipate the energy from the collapsing magnetic field at deactivation, which would otherwise generate a voltage spike dangerous to circuit components. Some automotive relays already include that diode inside the relay case. Alternatively a contact protection network, consisting of a capacitor and resistor in series, may absorb the surge. If the coil is designed to be energized with AC, a small copper ring can be crimped to the end of the solenoid. This "shading ring" creates a small out-of-phase current, which increases the minimum pull on the armature during the AC cycle.[1]
By analogy with the functions of the original electromagnetic device, a solid-state relay is made with a thyristor or other solid-state switching device. To achieve electrical isolation an optocoupler can be used which is a light-emitting diode (LED) coupled with a photo transistor.

Types of relay
¢ Latching relay

A latching relay has two relaxed states (bistable). These are also called 'keep' or 'stay' relays. When the current is switched off, the relay remains in its last state. This is achieved with a solenoid operating a ratchet and cam mechanism, or by having two opposing coils with an over-center spring or permanent magnet to hold the armature and contacts in position while the coil is relaxed, or with a remnant core. In the ratchet and cam example, the first pulse to the coil turns the relay on and the second pulse turns it off. In the two coil example, a pulse to one coil turns the relay on and a pulse to the opposite coil turns the relay off. This type of relay has the advantage that it consumes power only for an instant, while it is being switched, and it retains its last setting across a power outage.
¢ Reed relay
A reed relay has a set of contacts inside a vacuum or inert gas filled glass tube, which protects the contacts against atmospheric corrosion. The contacts are closed by a magnetic field generated when current passes through a coil around the glass tube. Reed relays are capable of faster switching speeds than larger types of relays, but have low switch current and voltage ratings. See also reed switch.
¢ Mercury-wetted relay

A mercury-wetted reed relay is a form of reed relay in which the contacts are wetted with mercury. Such relays are used to switch low-voltage signals (one volt or less) because of its low contact resistance, or for high-speed counting and timing applications where the mercury eliminates contact bounce. Mercury wetted relays are position-sensitive and must be mounted vertically to work properly. Because of the toxicity and expense of liquid mercury, these relays are rarely specified for new equipment. See also mercury switch.
¢ Polarized relay

A Polarized Relay placed the armature between the poles of a permanent magnet to increase sensitivity. Polarized relays were used in middle 20th Century telephone exchanges to detect faint pulses and correct telegraphic distortion. The poles were on screws, so a technician could first adjust them for maximum sensitivity and then apply a bias spring to set the critical current that would operate the relay.
¢ Machine tool relay

A machine tool relay is a type standardized for industrial control of machine tools, transfer machines, and other sequential control. They are characterized by a large number of contacts (sometimes extendable in the field) which are easily converted from normally-open to normally-closed status, easily replaceable coils, and a form factor that allows compactly installing many relays in a control panel. Although such relays once were the backbone of automation in such industries as automobile assembly, the programmable logic controller (PLC) mostly displaced the machine tool relay from sequential control applications.
¢ Contactor relay

A contactor is a very heavy-duty relay used for switching electric motors and lighting loads. High-current contacts are made with alloys containing silver. The unavoidable arcing causes the contacts to oxidize and silver oxide is still a good conductor. Such devices are often used for motor starters. A motor starter is a contactor with overload protection devices attached. The overload sensing devices are a form of heat operated relay where a coil heats a bi-metal strip, or where a solder pot melts, releasing a spring to operate auxiliary contacts. These auxiliary contacts are in series with the coil. If the overload senses excess current in the load, the coil is de-energized. Contactor relays can be extremely loud to operate, making them unfit for use where noise is a chief concern.
¢ Solid-state relay

Solid state relay, which has no moving parts 25 amp or 40 amp solid state contactors
A solid state relay (SSR) is a solid state electronic component that provides a similar function to an electromechanical relay but does not have any moving components, increasing long-term reliability. With early SSR's, the tradeoff came from the fact that every transistor has a small voltage drop across it. This voltage drop limited the amount of current a given SSR could handle. As transistors improved, higher current SSR's, able to handle 100 to 1,200 amps, have become commercially available. Compared to electromagnetic relays, they may be falsely triggered by transients.
¢ Solid state contactor relay

A solid state contactor is a very heavy-duty solid state relay, including the necessary heat sink, used for switching electric heaters, small electric motors and lighting loads; where frequent on/off cycles are required. There are no moving parts to wear out and there is no contact bounce due to vibration. They are activated by AC control signals or DC control signals from Programmable logic controller (PLCs), PCs, Transistor-transistor logic (TTL) sources, or other microprocessor controls.
¢ Buchholz relay

A Buchholz relay is a safety device sensing the accumulation of gas in large oil-filled transformers, which will alarm on slow accumulation of gas or shut down the transformer if gas is produced rapidly in the transformer oil.
¢ Forced-guided contacts relay

A forced-guided contacts relay has relay contacts that are mechanically linked together, so that when the relay coil is energized or de-energized, all of the linked contacts move together. If one set of contacts in the relay becomes immobilized, no other contact of the same relay will be able to move. The function of forced-guided contacts is to enable the safety circuit to check the status of the relay. Forced-guided contacts are also known as "positive-guided contacts", "captive contacts", "locked contacts", or "safety relays".
¢ Overload protection relay

One type of electric motor overload protection relay is operated by a heating element in series with the electric motor . The heat generated by the motor current operates a bi-metal strip or melts solder, releasing a spring to operate contacts. Where the overload relay is exposed to the same environment as the motor, a useful though crude compensation for motor ambient temperature is provided.



The most commonly used Character based LCDs are based on Hitachi's HD44780 controller or other which are compatible with HD44580. In this tutorial, we will discuss about character based LCDs, their interfacing with various microcontrollers, various interfaces (8-bit/4-bit), programming, special stuff and tricks you can do with these simple looking LCDs which can give a new look to your application.

Pin Description

The most commonly used LCDâ„¢s found in the market today are 1 Line, 2 Line or 4 Line LCDs which have only 1 controller and support at most of 80 characters, whereas LCDs supporting more than 80 characters make use of 2 HD44780 controllers.

Most LCDs with 1 controller has 14 Pins and LCDs with 2 controller has 16 Pins (two pins are extra in both for back-light LED connections). Pin description is shown in the table below.

Pin No. Name Description
Pin no. 1 VSS Power supply (GND)
Pin no. 2 VCC Power supply (+5V)
Pin no. 3 VEE Contrast adjust
Pin no. 4 RS 0 = Instruction input
1 = Data input
Pin no. 5 R/W 0 = Write to LCD module
1 = Read from LCD module
Pin no. 6 EN Enable signal
Pin no. 7 D0 Data bus line 0 (LSB)
Pin no. 8 D1 Data bus line 1
Pin no. 9 D2 Data bus line 2
Pin no. 10 D3 Data bus line 3
Pin no. 11 D4 Data bus line 4
Pin no. 12 D5 Data bus line 5
Pin no. 13 D6 Data bus line 6
Pin no. 14 D7 Data bus line 7 (MSB)

DDRAM - Display Data RAM

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 X 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. So whatever you send on the DDRAM is actually displayed on the LCD. For LCDs like 1x16, only 16 characters are visible, so whatever you write after 16 chars is written in DDRAM but is not visible to the user.

CGROM - Character Generator ROM

Now you might be thinking that when you send an ASCII value to DDRAM, how the character is displayed on LCD So the answer is CGROM. The character generator ROM generates 5 x 8 dot or 5 x 10 dot character patterns from 8-bit character codes (see Figure 5 and Figure 6 for more details). It can generate 208 5 x 8 dot character patterns and 32 5 x 10 dot character patterns. User defined character patterns are also available by mask-programmed ROM.

As you can see in both the code maps, the character code from 0x00 to 0x07 is occupied by the CGRAM characters or the user defined characters. If user wants to display the fourth custom character then the code to display it is 0x03 i.e. when user sends 0x03 code to the LCD DDRAM then the fourth user created character or pattern will be displayed on the LCD.
CGRAM - Character Generator RAM

As clear from the name, CGRAM area is used to create custom characters in LCD. In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written, and for 5 x 10 dots, four character patterns can be written.

BF - Busy Flag

Busy Flag is a status indicator flag for LCD. When we send a command or data to the LCD for processing, this flag is set (i.e. BF =1) and as soon as the instruction is executed successfully this flag is cleared (BF = 0). This is helpful in producing and exact amount of delay for the LCD processing.

To read Busy Flag, the condition RS = 0 and R/W = 1 must be met and The MSB of the LCD data bus (D7) act as busy flag. When BF = 1 means LCD is busy and will not accept next command or data and BF = 0 means LCD is ready for the next command or data to process.

Instruction Register (IR) and Data Register (DR)

There are two 8-bit registers in HD44780 controller Instruction and Data register. Instruction register corresponds to the register where you send commands to LCD e.g. LCD shift command, LCD clear, LCD address etc. and Data register is used for storing data which is to be displayed on LCD. When send the enable signal of the LCD is asserted, the data on the pins is latched in to the data register and data is then moved automatically to the DDRAM and hence is displayed on the LCD.
Data Register is not only used for sending data to DDRAM but also for CGRAM, the address where you want to send the data, is decided by the instruction you send to LCD.

4-bit programming of LCD

In 4-bit mode the data is sent in nibbles, first we send the higher nibble and then the lower nibble. To enable the 4-bit mode of LCD, we need to follow special sequence of initialization that tells the LCD controller that user has selected 4-bit mode of operation. We call this special sequence as resetting the LCD. Following is the reset sequence of LCD.
Wait for about 20mS
Send the first init value (0x30)
Wait for about 10mS
Send second init value (0x30)
Wait for about 1mS
Send third init value (0x30)
Wait for 1mS
Select bus width (0x30 - for 8-bit and 0x20 for 4-bit)
Wait for 1mS

The busy flag will only be valid after the above reset sequence. Usually we do not use busy flag in 4-bit mode as we have to write code for reading two nibbles from the LCD. Instead we simply put a certain amount of delay usually 300 to 600uS. This delay might vary depending on the LCD you are using, as you might have a different crystal frequency on which LCD controller is running. So it actually depends on the LCD module you are using.

In 4-bit mode, we only need 6 pins to interface an LCD. D4-D7 are the data pins connection and Enable and Register select are for LCD control pins. We are not using Read/Write (RW) Pin of the LCD, as we are only writing on the LCD so we have made it grounded permanently. If you want to use it, then you may connect it on your controller but that will only increase another pin and does not make any big difference. Potentiometer RV1 is used to control the LCD contrast. The unwanted data pins of LCD i.e. D0-D3 are connected to ground.

Sending data/command in 4-bit Mode
We will now look into the common steps to send data/command to LCD when working in 4-bit mode. In 4-bit mode data is sent nibble by nibble, first we send higher nibble and then lower nibble. This means in both command and data sending function we need to separate the higher 4-bits and lower 4-bits.

The common steps are:

Mask lower 4-bits
Send to the LCD port
Send enable signal
Mask higher 4-bits
Send to LCD port
Send enable signal



Mainly the block diagram consists of following parts:

¢ Power supply circuit
¢ ARM controller
¢ RFID Module
¢ Relay

This project and implimentation Robust and efficient password authenticated key agreement using smart card for campus management will give the best and security solution for entry of authenticated people into restricted and security areas. This project and implimentation will consists of RFID module(Tag as well as the reader ), keypad, and ARM7 based microcontroller module. i.e., LPC2148. The students are given with unique RFID tag. And at the time of issuing the tag person details will be added to the database of the LPC2148 microcontroller which is stored in its flash memory.
Whenever the person wants to enter the campus he has to put the tag at the entrance of the campus. RFID reader which is connected to the microcontroller module will read the data and gives the information to the microcontroller module. After that using the keypad the person has to enter the password provided to him. Then microcontroller module will compare the passwords of the person entered with the password of the this person which is stored in its data base. If he is authenticated to enter in to the campus then the gate will be open which is demonstrated here with glowing of LED for authenticated persons.

Hardware & Schematic:-


A variable regulated power supply, also called a variable bench power supply, is one where you can continuously adjust the output voltage to your requirements. Varying the output of the power supply is the recommended way to test a project and implimentation after having double checked parts placement against circuit drawings and the parts placement guide.
This type of regulation is ideal for having a simple variable bench power supply. Actually this is quite important because one of the first project and implimentations a hobbyist should undertake is the construction of a variable regulated power supply. While a dedicated supply is quite handy ,it's much handier to have a variable supply on hand, especially for testing.
Mainly the ARM controller needs 3.3 volt power supply. To use these parts we need to build a regulated 3.3 volt source. Usually you start with an unregulated power To make a 3.3 volt power supply, we use a LM317 voltage regulator IC (Integrated Circuit). The IC is shown below.



Vout range 1.25V - 37V
Vin - Vout difference 3V - 40V
Operation ambient temperature 0 - 125°C
Output Imax <1.5A
Minimum Load Currentmax 10mA

A current-limiting circuit constructed with LM317

Part pinout of LM317 showing its constant voltage reference
LM317 is the standard part number for an integrated three-terminal adjustable linear voltage regulator. LM317 is a positive voltage regulator supporting input voltage of 3V to 40V and output voltage between 1.25V and 37V. A typical current rating is 1.5A although several lower and higher current models are available. Variable output voltage is achieved by using a potentiometer or a variable voltage from another source to apply a control voltage to the control terminal. LM317 also has a built-in current limiter to prevent the output current from exceeding the rated current, and LM317 will automatically reduce its output current if an overheat condition occurs under load. LM317 is manufactured by many companies, including National Semiconductor, Fairchild Semiconductor, and STMicroelectronics.
Although LM317 is an adjustable regulator, it is sometimes preferred for high-precision fixed voltage applications instead of the similar LM78xx devices because the LM317 is designed with superior output tolerances. For a fixed voltage application, the control pin will typically be biased with a fixed resistor network, a Zener diode network, or a fixed control voltage from another source. Manufacturer datasheets provide standard configurations for achieving various design applications, including the use of a pass transistor to achieve regulated output currents in excess of what the LM317 alone can provide.
LM317 is available in a wide range of package forms for different applications including heat sink mounting and surface-mount applications. Common form factors for high-current applications include TO-220 and TO-3. LM317 is capable of dissipating a large amount of heat at medium to high current loads and the use of a heat sink is recommended to maximize the lifespan and power-handling capability.
LM337 is the negative voltage complement to LM317 and the specifications and function are essentially identical, except that the regulator must receive a control voltage and act on an input voltage that are below the ground reference point instead of above it.


#include <LPC21xx.h>
#include <string.h>
#include "lcd.h"
#include "uart.h"
#include "switch.h"

int admin_mode(void);
int user_mode(void);
int compare(unsigned char *);
int receive_char (void);
unsigned char value[5][12];
int main()
    unsigned char sw;
    unsigned char *str1="RFID based";
    unsigned char *str2="Campus Managemnt";
unsigned char *str3="Invalid option";
    int i;


        sw = options();
        if(sw == 1)
        else if(sw == 2)

int admin_mode(void)
    int i,j,x,z;
    unsigned char *str0 = " Enter";
    unsigned char *str1 = "card bar code:";
    unsigned char *str2 = "Continue ";
    unsigned char *str3 = " 1.yes 2.No";
    unsigned char *str9 = "ur option :";
    unsigned char sw = 0x01;
    x = Check_Pwd();
    if(x == 1)
        return 1;
    else if(x == 0)
            for(i=0;((i<5) && (sw == 1));i++)
                    while(!(U0LSR & 0x01));
                        while(!(U0LSR & 0x01));
                else if(i == 0)
                        while(!(U0LSR & 0x01));


                sw = get_option();
    return 0;
int user_mode(void)
    int x;
    unsigned char c;
    while(!(U0LSR & 0x01));
    c = U0RBR;
    x = receive_char();
    if(x == 1)
        return 1;
    return 0;

int compare(unsigned char *string)
    unsigned char *str0 = "Accepted";
    unsigned char *str1 = "Denied";
    unsigned int z = 0;
    int i;

        if(!(strcmp((const char *)string,(const char *)value[i])))
            z = 1;
    if(z == 1)
        return 0;
        return 1;
int receive_char (void)
    int i,x;
    unsigned char value[11];
    unsigned char *str0 = " Enter";
    unsigned char *str1 = "card bar code:";
    unsigned char *str2 = "wrong PWD";
    unsigned char *string;
    IO0DIR |= 0x00000800;
    IO0SET |= 0x00000800;
    string = value;
        while(!(U0LSR & 0x01));


    x = compare(string);
    if(x == 0)
        x = Check_Pwd();
        if(x == 1)
            return 1;
        IO0CLR |= 0x00000800;
        IO0SET |= 0x00000800;
    else if(x == 1)
        return 1;
    return 0;        
/* LCD routines for OLIMEX LPC-2148 */
/* 16x2 Character LCD 1602K */
/* 4-bit mode operation     */
/*Devoloped by NARESH & SURESH */
#define LCD_D4 0x10 //P0.04     /*THESE DATA LINES ARE INITIALIZED TO PORT 0.4 TO 0.7 */
#define LCD_D5 0x20 //P0.05
#define LCD_D6 0x40 //P0.06
#define LCD_D7 0x80 //P0.07
#define LCD_EN 0x400000 //P0.22
#define LCD_RS 0x800000 //P0.23

#define LCD_DATA (LCD_D4|LCD_D5|LCD_D6|LCD_D7)

#define LCD_GPIO_SEL0 0x000000F0 //MASK for P0.04-P0.07
#define LCD_GPIO_SEL1 0x00C00000 //MASK for P0.22-P0.24
/* Functions Header */
/* internal I/O functions */
#define lcd_rs_set() IO0SET |= LCD_RS
#define lcd_rs_clr() IO0CLR |= LCD_RS
#define lcd_en_set() IO0SET |= LCD_EN
#define lcd_en_clr() IO0CLR |= LCD_EN
/* wait until lcd controller is free */
void lcd_wait(void);
void lcd_out_data4(unsigned char);
void lcd_write_nibbles(unsigned char);
void lcd_write_control(unsigned char);

/* initialize both the GPIO of lpc and LCD */
void lcd_init(void);

#define lcd_clear() lcd_write_control(0x01)
#define lcd_cursor_home() lcd_write_control(0x02)

#define lcd_display_on() lcd_write_control(0x0E)
#define lcd_display_off() lcd_write_control(0x08)

#define lcd_cursor_blink() lcd_write_control(0x0F)
#define lcd_cursor_on() lcd_write_control(0x0E)
#define lcd_cursor_off() lcd_write_control(0x0C)

#define lcd_cursor_left() lcd_write_control(0x10)
#define lcd_cursor_right() lcd_write_control(0x14)
#define lcd_display_sleft() lcd_write_control(0x18)
#define lcd_display_sright() lcd_write_control(0x1C)
#define lcd_next_line() lcd_write_control(0xC0)    

#define lcd_First_line() lcd_write_control(0x80)     //Oct23
#define lcd_Second_line() lcd_write_control(0xC0)     //Oct23
/* put a character out to lcd */
void lcd_putchar(unsigned char);
/* print a string */
void lcd_print(unsigned char*);

void lcd_dec(unsigned char);

void lcd_dec_nibble(unsigned char);
void lcd_dec_nibble1(unsigned char);
void lcd_dec_int(unsigned int num);

#define RSIR (*((volatile unsigned char *) 0xE01FC180))

void lcd_wait(void)
int loop=30000;


void lcd_out_data4(unsigned char val)
IO0SET |= (val<<8);
void lcd_write_nibbles(unsigned char val)
     unsigned char temp;
//higher-order byte


//lower-order byte


void lcd_write_control(unsigned char val){

void lcd_init(void){

/* we only work on OUTPUT so far */

/* IO init complete, init LCD */

/* init 4-bit ops*/
//wait VDD raise > 4.5V

//dummy inst





void lcd_putchar(unsigned char c)

void lcd_print(unsigned char *str){

    unsigned char ch;
    {    ch=*str;
void lcd_dec(unsigned char num)         /* TRANSFERS DECIMAL DATA TO LCD */
    unsigned char x,d1,d2;
     d2= x%10;

void lcd_dec_nibble(unsigned char num) {
    unsigned char d1;
//     x=num/10;
//     d2= x%10;


void lcd_dec_nibble1(unsigned char num) {
    unsigned char d1,x,d2;
     d2= x%10;

void lcd_dec_int(unsigned int num)         /* TRANSFERS DECIMAL DATA TO LCD */
    unsigned char x,d1,d2;
     d2= x%10;
unsigned char options(void);
void Receive_Pwd(void);
unsigned char get_option(void);
int Check_Pwd(void);

unsigned long Read_IOPin = 0x00;
unsigned char IO_Val = 0x00;
unsigned char Pswd[5];
//Gives the options......and receives the one option from user or admin
unsigned char options(void)
    unsigned char *str1 = "1.Administrator";
    unsigned char *str2 = "2.User";
    unsigned char *str3 = "Choose one mode";
    unsigned char *str4 = "option : ";
    unsigned char sw;
    int i;


    sw = get_option();

void Receive_Pwd(void)
        unsigned int cnt = 0;
        unsigned char sw = 0x00;
        unsigned char i = 0x00;
        unsigned char *str1 = "Enter ur PWD:";

        for(cnt = 0; cnt < 3; cnt ++)

        while( (IOPIN1 & 0x00010000) && (IOPIN1 & 0x00020000) && (IOPIN1 & 0x00040000) );
        Read_IOPin = IOPIN1;     
        IO_Val = ( (Read_IOPin >> 16) & 0x07);
        if(i > 2)
            i = 0;


            case 0x06:                      // p1.16 is pressed        
                Pswd[i++] = 0x06;
                sw = 1;                     

            case 0x05:                       // p1.17 is pressed
                Pswd[i++] = 0x05;
                sw = 2;                     

            case 0x03:                      //// p1.18 is pressed    
                Pswd[i++] = 0x03;
                sw = 3;                     
} // End of Receive_Pwd()...                
int Check_Pwd(void)

    unsigned char *str0 = "Accepted";
    unsigned char *str1 = "Wrong Pwd";

    if((Pswd[0] == 0x06) && (Pswd[1] == 0x05) && (Pswd[2] == 0x03) ) // Correct Password
        return 0;
    {                                 //Wrong password
        return 1;
}    // End of Check_Pwd()...    

unsigned char get_option(void)
        unsigned char sw = 0x00;

        while( (IOPIN1 & 0x00010000) && (IOPIN1 & 0x00020000) && (IOPIN1 & 0x00040000) );
        Read_IOPin = IOPIN1;     
        IO_Val = ( (Read_IOPin >> 16) & 0x07);

            case 0x06:                      // p1.16 is pressed        
                        sw = 1;

            case 0x05:                       // p1.17 is pressed
                        sw = 2;

        return (sw);        
void Send_String_Uart0(unsigned char *);
void Send_char_Uart0(unsigned char);
void Send_char_Uart1(unsigned char );
void Send_String_Uart1(unsigned char* );
void init_serial_gsm(void);
unsigned char getchar1(void);
unsigned char getchar0(void);
void init_serial(void)

    PINSEL0 |= 0x00050005;
    U0LCR = 0x03;
    U1LCR = 0x03;
    U0DLL = 92;
    U1DLL = 92;
    U0LCR = 0x01;
    U1LCR = 0X01;
    U0DLM = 0;
    U1DLM = 0;
    U0FCR = 1;
    U1FCR = 1;
void Send_String_Uart0(unsigned char* string)

        while(!(U0LSR & 0x20)) ;
        U0THR = *string;

void Send_String_Uart1(unsigned char* string)

        while(!(U1LSR & 0x10)) ;
        U1THR = *string;

void Send_char_Uart0(unsigned char ch)

    while(!(U0LSR & 0x10)) ;
    U0THR = ch;

void Send_char_Uart1(unsigned char ch)

    while(!(U1LSR & 0x10)) ;
    U1THR = ch;

void delay()
    int i;

unsigned char getchar0(void)
while (!(U0LSR & 0x02));
return (U0RBR);

unsigned char getchar1 (void)
     while (!(U1LSR & 0x02));
     return (U1RBR);

Introduction to Micro vision Keil (IDE)

Keil is a cross compiler. So first we have to understand the concept of compilers and cross compilers. After then we shall learn how to work with keil.

Concept of compiler: -

Compilers are programs used to convert a High Level Language to object code. Desktop compilers produce an output object code for the underlying microprocessor, but not for other microprocessors. I.E the programs written in one of the HLL like ËœCâ„¢ will compile the code to run on the system for a particular processor like x86 (underlying microprocessor in the computer). For example compilers for Dos platform is different from the Compilers for Unix platform

So if one wants to define a compiler then compiler is a program that translates source code into object code. The compiler derives its name from the way it works, looking at the entire piece of source code and collecting and reorganizing the instruction. See there is a bit little difference between compiler and an interpreter. Interpreter just interprets whole program at a time while compiler analyzes and execute each line of source code in succession, without looking at the entire program.

The advantage of interpreters is that they can execute a program immediately. Secondly programs produced by compilers run much faster than the same programs executed by an interpreter. However compilers require some time before an executable program emerges. Now as compilers translate source code into object code, which is unique for each type of computer, many compilers are available for the same language.

Concept of cross compiler: -

A cross compiler is similar to the compilers but we write a program for the target processor (like 8051 and its derivatives) on the host processors (like computer of x86)
It means being in one environment you are writing a code for another environment is called cross development. And the compiler used for cross development is called cross compiler

So the definition of cross compiler is a compiler that runs on one computer but produces object code for a different type of computer. Cross compilers are used to generate software that can run on computers with a new architecture or on special-purpose devices that cannot host their own co
Use Search at wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion
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Posts: 610
Joined: Jun 2010
24-06-2010, 11:46 AM

Concept of cross compiler: -

A cross compiler is similar to the compilers but we write a program for the target processor (like 8051 and its derivatives) on the host processors (like computer of x86)
It means being in one environment you are writing a code for another environment is called cross development. And the compiler used for cross development is called cross compiler

So the definition of cross compiler is a compiler that runs on one computer but produces object code for a different type of computer. Cross compilers are used to generate software that can run on computers with a new architecture or on special-purpose devices that cannot host their own compilers. Cross compilers are very popular for embedded development, where the target probably couldn't run a compiler. Typically an embedded platform has restricted RAM, no hard disk, and limited I/O capability. Code can be edited and compiled on a fast host machine (such as a PC or Unix workstation) and the resulting executable code can then be downloaded to the target to be tested. Cross compilers are beneficial whenever the host machine has more resources (memory, disk, I/O etc) than the target. Keil C Compiler is one such compiler that supports a huge number of host and target combinations. It supports as a target to 8 bit microcontrollers like Atmel and Motorola etc.

Why do we need cross compiler

There are several advantages of using cross compiler. Some of them are described as follows
¢ By using this compilers not only can development of complex embedded systems be completed in a fraction of the time, but reliability is improved, and maintenance is easy.
¢ Knowledge of the processor instruction set is not required.
¢ A rudimentary knowledge of the 8051™s memory architecture is desirable but not necessary.
¢ Register allocation and addressing mode details are managed by the compiler.
¢ The ability to combine variable selection with specific operations improves program readability.
¢ Keywords and operational functions that more nearly resemble the human thought process can be used.
¢ Program development and debugging times are dramatically reduced when compared to assembly language programming.
¢ The library files that are supplied provide many standard routines (such as formatted output, data conversions, and floating-point arithmetic) that may be incorporated into your application.
¢ Existing routine can be reused in new programs by utilizing the modular programming techniques available with C.
¢ The C language is very portable and very popular. C compilers are available for almost all target systems. Existing software investments can be quickly and easily converted from or adapted to other processors or environments.

Now after going through the concept of compiler and cross compilers lets we start with Keil C cross compiler.

Keil C cross compiler: -

Keil is a German based Software development company. It provides several development tools like
¢ IDE (Integrated Development environment)
¢ Project Manager
¢ Simulator
¢ Debugger
¢ C Cross Compiler, Cross Assembler, Locator/Linker
Keil Software provides you with software development tools for the ARM microcontrollers. With these tools, you can generate embedded applications for the multitude of ARM derivatives. Keil provides following tools for ARM development
1. ARM Optimizing C Cross Compiler,
2. Macro Assembler,
3. ARM Utilities (linker, object file converter, library manager),
4. Source-Level Debugger/Simulator,
5. µVision for Windows Integrated Development Environment.
The keil ARM tool kit includes three main tools, assembler, compiler and linker.
An assembler is used to assemble your ARM assembly program
A compiler is used to compile your C source code into an object file
A linker is used to create an absolute object module suitable for your in-circuit emulator.

ARM project and implimentation development cycle: -

These are the steps to develop ARM project and implimentation using keil
1. Create source files in C or assembly.
2. Compile or assemble source files.
3. Correct errors in source files.
4. Link object files from compiler and assembler.
5. Test linked application.


The project and implimentation ROBUST AND EFFICIENT PASSWORD-AUTHENTICATED KEY AGREEMENT USING SMART CARDS FOR CAMPUS MANAGEMENT has been successfully designed and tested. It has been developed by integrating features of all the hardware components used. Presence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit.
Secondly, using highly advanced ICâ„¢s and with the help of growing technology the project and implimentation has been successfully implemented.



The 8051 Micro controller and Embedded Systems
-Muhammad Ali Mazidi
-Janice Gillispie Mazidi

The 8051 Micro controller Architecture, Programming & Applications
-Kenneth J.Ayala

Fundamentals Of Micro processors and Micro computers

Micro processor Architecture, Programming & Applications
-Ramesh S.Gaonkar

Electronic Components

Wireless Communications
- Theodore S. Rappaport

Mobile Tele Communications
- William C.Y. Lee
ARM System Developerâ„¢s Guide
-Andrew N.SLOSS
-Domenic SYMES

References on the Web:
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20-07-2010, 12:29 PM

please how do one go about the interphasing?
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25-07-2010, 03:43 PM

no circuit diagram for the interfacing?
seminar ideas
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04-07-2012, 09:52 AM

to get information about the topic"Secure and Efficient password based Authenticated key exchange protocol for two serv" full report ppt and related topic refer the link bellow



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